公开(公告)号：US20080143391A1

公开(公告)日：2008-06-19

申请号：US12040805

申请日：2008-02-29

申请人： Klass BULT ,  Rudy VAN DER PLASSCHE ,  Jan MULDER

发明人： Klass BULT ,  Rudy VAN DER PLASSCHE ,  Jan MULDER

IPC分类号： H03K3/45 ,  H03L7/00

CPC分类号： H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

摘要： In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

摘要翻译： 在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到 锁存电路端口。 这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。