公开(公告)号：US09660844B2

公开(公告)日：2017-05-23

申请号：US14938163

申请日：2015-11-11

Applicant: Rambus Inc.

Inventor： Brian Leibowitz ,  Jaeha Kim

IPC: H04L25/03 ,  H03M1/36 ,  H03M1/12 ,  H03M1/00

CPC classification number: H04L25/03057 ,  H03M1/004 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/362 ,  H04L25/03146 ,  H04L25/03885 ,  H04L2025/03363 ,  H04L2025/03369

Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

公开(公告)号：US09214912B2

公开(公告)日：2015-12-15

申请号：US14684023

申请日：2015-04-10

Applicant: Massachusetts Institute of Technology

Inventor： Hae-Seung Lee

IPC: H03M1/36 ,  H03G3/00 ,  H03F3/00 ,  H03F3/45 ,  H03M1/12

CPC classification number: H03G3/008 ,  H03F3/005 ,  H03F3/45179 ,  H03F2200/129 ,  H03F2203/45156 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/362

Abstract: Switched capacitor circuits and charge transfer methods include a sampling phase and a transfer phase. Circuits and methods are implemented via a plurality of switches, a set of at least two capacitors, at least one buffer amplifier, and an operational amplifier. In one example, during the sampling phase at least one input voltage is sampled, and during the transfer phase at least a first reference voltage provided by the at least one buffer amplifier is subtracted from the at least one input voltage using the operational amplifier. The same set of at least two capacitors may be used in both the sampling phase and the transfer phase.

Abstract translation: 开关电容器电路和电荷转移方法包括采样阶段和转移阶段。 电路和方法通过多个开关，一组至少两个电容器，至少一个缓冲放大器和运算放大器来实现。 在一个示例中，在采样阶段期间对至少一个输入电压进行采样，并且在传送阶段期间，使用运算放大器从至少一个输入电压减去由至少一个缓冲放大器提供的至少第一参考电压。 在采样阶段和转移阶段都可以使用同一组至少两个电容器。

公开(公告)号：US08410820B2

公开(公告)日：2013-04-02

申请号：US13026904

申请日：2011-02-14

Applicant: Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

Inventor： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

IPC: G01R19/00 ,  G11C7/00 ,  H03K3/45

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

公开(公告)号：US20120314756A1

公开(公告)日：2012-12-13

申请号：US13578217

申请日：2010-11-24

Applicant: Brian S. Leibowitz ,  Jaeha Kim

Inventor： Brian S. Leibowitz ,  Jaeha Kim

IPC: H04L27/01

CPC classification number: H04L25/03057 ,  H03M1/004 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/362 ,  H04L25/03146 ,  H04L25/03885 ,  H04L2025/03363 ,  H04L2025/03369

Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Abstract translation: 在相同符号时间内，判决反馈均衡器（DFE）对M个参考采样模拟输入信号以产生M个推测采样。 在DFE中选择逻辑然后解码先前为先前符号时间分辨的N个比特，以选择M个推测样本之一作为当前分辨比特。 当前解析的位然后被存储为最近以前解析的位，以准备下一个符号时间。 选择逻辑可以是可编程的，以适应过程，环境和系统变化。

公开(公告)号：US07999713B2

公开(公告)日：2011-08-16

申请号：US12530521

申请日：2008-03-13

Applicant: Jean-Alain Nicolas ,  Richard Morisson

Inventor： Jean-Alain Nicolas ,  Richard Morisson

IPC: H03M1/12

CPC classification number: H03M1/362 ,  H03M1/0682

Abstract: The invention relates to fast, high resolution, analog digital converters, and more particularly those which possess at least one conversion stage of “flash” type. The converter according to the invention uses N differential amplifiers with four inputs. The amplifier of rank j receives the input voltage to be converted Vep−Ven on two first inputs, and a reference potential difference on two other inputs. The reference potential difference is obtained between two taps of networks of resistors that are identical operating in parallel and supplied between a high voltage source and a low current source; the taps for an amplifier are respectively a tap Pj of rank j of a first network and a tap P′N−j+1 of rank N−j+1 of a second network. This reduces the first and second order non-linearity effects due to the fact that the differential amplifiers consume an input current tapped off from the networks of resistors.

Abstract translation: 本发明涉及快速，高分辨率的模拟数字转换器，更具体地涉及具有至少一个“闪光”型转换级的转换器。 根据本发明的转换器使用具有四个输入的N个差分放大器。 秩j的放大器在两个第一输入端接收要转换的输入电压Vep-Ven，另外两个输入端接收参考电位差。 在并联运行并且在高电压源和低电流源之间提供的电阻器的两个抽头网络之间获得参考电位差; 放大器的抽头分别是第一网络的级别j的抽头Pj和第二网络的级别N-j + 1的抽头P'N-j + 1。 由于差分放大器消耗从电阻网络中抽出的输入电流，因此这降低了第一和第二阶非线性效应。

公开(公告)号：US20110133967A1

公开(公告)日：2011-06-09

申请号：US13026904

申请日：2011-02-14

Applicant: Klaas BULT ,  Rudy VAN DE PLASSCHE ,  Jan MULDER

Inventor： Klaas BULT ,  Rudy VAN DE PLASSCHE ,  Jan MULDER

IPC: H03M1/06 ,  H03K3/00 ,  H03K3/02 ,  H03M1/34

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract translation: 在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到 锁存电路端口。 这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。

公开(公告)号：US07911365B2

公开(公告)日：2011-03-22

申请号：US12656055

申请日：2010-01-14

Applicant: Jun Cao ,  Afshin Momtaz

Inventor： Jun Cao ,  Afshin Momtaz

IPC: H03M1/10

CPC classification number: H03M1/1061 ,  H03M1/362

Abstract: An analog-to-digital converter (ADC) is provided. The ADC includes a reference voltage generator configured to generate reference voltages, an analog to digital converter core configured to receive an input signal and the reference voltages and to generate a digital signal representative of the input signal, the digital signal having a number of bits, and a controller configured to determine a quality of the input signal, and, based on a quality of the input signal, to control the number of bits of the digital signal and values of the reference voltages.

Abstract translation: 提供了一个模拟 - 数字转换器（ADC）。 ADC包括被配置为产生参考电压的参考电压发生器，被配置为接收输入信号和参考电压并且产生代表输入信号的数字信号的模数转换器内核，数字信号具有多个位， 以及控制器，被配置为确定输入信号的质量，并且基于输入信号的质量来控制数字信号的位数和参考电压的值。

公开(公告)号：US20110063153A1

公开(公告)日：2011-03-17

申请号：US12948775

申请日：2010-11-18

Applicant: Tzung-Hung Kang

Inventor： Tzung-Hung Kang

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/367 ,  H03M1/1295 ,  H03M1/183 ,  H03M1/362

Abstract: A data readout system with non-uniform resolution has a pick up head for reading data stored in an optical disc and generating an analog signal, a reference voltage unit for producing a plurality of reference voltage levels, wherein voltage differences between two adjacent reference voltage levels are not all the same, a plurality of comparators for comparing the reference voltage levels with the analog signal and generating comparison results, and an encoder for encoding the comparison results into a digital signal.

Abstract translation: 具有不均匀分辨率的数据读出系统具有用于读取存储在光盘中的数据并产生模拟信号的拾取头，用于产生多个参考电压电平的参考电压单元，其中两个相邻参考电压电平之间的电压差 多个比较器，用于将参考电压电平与模拟信号进行比较并产生比较结果;以及编码器，用于将比较结果编码为数字信号。

公开(公告)号：US20100097260A1

公开(公告)日：2010-04-22

申请号：US12582431

申请日：2009-10-20

Applicant: Yuji NAKAJIMA

Inventor： Yuji NAKAJIMA

IPC: H03M1/36

CPC classification number: H03M1/1023 ,  H03M1/141 ,  H03M1/205 ,  H03M1/362

Abstract: An analog-to-digital converter includes a first preamplifier receiving a first reference voltage and an input signal, a second preamplifier receiving a second reference voltage and the input signal, a first preamplifier calibrator placed for the first preamplifier and adjusting an input offset of the first preamplifier, a second preamplifier calibrator placed for the second preamplifier and adjusting an input offset of the second preamplifier, an interpolator placed between output terminals of the first and second preamplifiers and generating an interpolation signal having a voltage value between a first output signal from the first preamplifier and a second output signal from the second preamplifier, comparators receiving the first output signal, the second output signal or the interpolation signal and outputting a digital value based on the received signal, and comparator calibrators placed for at least comparators receiving the interpolation signal among the comparators and adjusting input offsets of the corresponding comparators.

Abstract translation: 模数转换器包括接收第一参考电压和输入信号的第一前置放大器，接收第二参考电压的第二前置放大器和输入信号，为第一前置放大器放置的第一前置放大器校准器， 第一前置放大器，用于第二前置放大器放置的第二前置放大器校准器，并且调整第二前置放大器的输入偏移;插入器，位于第一和第二前置放大器的输出端之间，并产生内插信号，该插值信号具有来自第一前置放大器的第一输出信号 第一前置放大器和来自第二前置放大器的第二输出信号，比较器接收第一输出信号，第二输出信号或内插信号，并且基于接收信号输出数字值，以及比较器校准器，用于至少比较器接收插值信号 比较和调整 g相应比较器的输入偏移量。

公开(公告)号：US20090135037A1

公开(公告)日：2009-05-28

申请号：US11945278

申请日：2007-11-27

Applicant: Nitin Agarwal ,  Ramesh Kumar Singh ,  Visvesvaraya A. Pentakota ,  Dantes John ,  Supreet Joshi

Inventor： Nitin Agarwal ,  Ramesh Kumar Singh ,  Visvesvaraya A. Pentakota ,  Dantes John ,  Supreet Joshi

IPC: H03M3/00

CPC classification number: H03M1/1023 ,  H03M1/0607 ,  H03M1/0624 ,  H03M1/167 ,  H03M1/362

Abstract: An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).

Abstract translation: 偏移校正电路检查管线模数转换器（ADC）的级的残留信号，以确定是否需要调整可能导致偏移误差的参数。 在一个实施例中，调整参数直到残差信号的最大范围等于预期范围。 在所描述的示例中，经调整的参数包括定时偏移误差（当ADC的分量对不同时间的输入信号进行采样时）和电压偏移误差（在产生子码的阶段中的子ADC的阈值电压 更改为下一个值）。