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公开(公告)号：US20080088493A1
公开(公告)日：2008-04-17
申请号：US11857417
申请日：2007-09-18
Applicant: Jan MULDER , Franciscus van der GOES , Jan WESTRA , Rudy van der PLASSCHE
Inventor： Jan MULDER , Franciscus van der GOES , Jan WESTRA , Rudy van der PLASSCHE
IPC: H03M1/66
CPC classification number: H03K17/04106 , H03M1/204 , H03M1/365
Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
Abstract translation: 电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。 放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。 第一多个开关将各个抽头连接到第一电容器的第二端子。 第二多个开关将各个抽头连接到第二电容器的第二端子。 通过控制第一和第二多个开关来内插输出电压。
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公开(公告)号：US07271755B2
公开(公告)日：2007-09-18
申请号：US10926407
申请日：2004-08-26
Applicant: Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
CPC classification number: H03K17/04106 , H03M1/204 , H03M1/365
Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
Abstract translation: 电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。 放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。 第一多个开关将各个抽头连接到第一电容器的第二端子。 第二多个开关将各个抽头连接到第二电容器的第二端子。 通过控制第一和第二多个开关来内插输出电压。
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公开(公告)号：US07616144B2
公开(公告)日：2009-11-10
申请号：US11857417
申请日：2007-09-18
Applicant: Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
IPC: H03M1/78
CPC classification number: H03K17/04106 , H03M1/204 , H03M1/365
Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
Abstract translation: 电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。 放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。 第一多个开关将各个抽头连接到第一电容器的第二端子。 第二多个开关将各个抽头连接到第二电容器的第二端子。 通过控制第一和第二多个开关来内插输出电压。
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公开(公告)号：US20080143391A1
公开(公告)日：2008-06-19
申请号：US12040805
申请日：2008-02-29
Applicant: Klass BULT , Rudy VAN DER PLASSCHE , Jan MULDER
Inventor： Klass BULT , Rudy VAN DER PLASSCHE , Jan MULDER
CPC classification number: H03K3/356043 , H03K3/012 , H03K3/35613 , H03K3/356182 , H03K3/356191 , H03M1/002 , H03M1/362
Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
Abstract translation: 在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到 锁存电路端口。 这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。
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