公开(公告)号：US5889443A

公开(公告)日：1999-03-30

申请号：US926756

申请日：1997-09-10

Applicant: Klaus J.o slashed.rgensen

Inventor： Klaus J.o slashed.rgensen

IPC: H03C3/09 ,  H03L7/193 ,  H03L7/197 ,  H04L27/12 ,  H03C3/00

CPC classification number: H03C3/0958 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/193 ,  H03L7/197 ,  H04L27/12

Abstract: A frequency synthesizing circuit has an input on which a bit flow is received, and an output on which a data-modulated output signal is supplied. The circuit moreover comprises a crystal oscillator supplying a reference clock signal, a phase-locked loop (PLL) having a VCO and a phase detector. The phase detector compares the data-modulated output signal with the reference clock signal and, in response to this, supplies an error signal by means of which the VCO output frequency is controlled. A compensation circuit, which receives a measure of the bit flow received, compensates the data-modulated output signal in the phase-locked loop in response to this before it is supplied to the phase detector.

Abstract translation: 频率合成电路具有接收位流的输入和提供数据调制输出信号的输出。 该电路还包括提供参考时钟信号的晶体振荡器，具有VCO的锁相环（PLL）和相位检测器。 相位检测器将数据调制输出信号与参考时钟信号进行比较，并且响应于此，提供控制VCO输出频率的误差信号。 接收到接收到的比特流的量度的补偿电路在被提供给相位检测器之前，根据该补偿电路补偿锁相环中的数据调制输出信号。