公开(公告)号：US20090051336A1

公开(公告)日：2009-02-26

申请号：US11842196

申请日：2007-08-21

申请人： Heimo Hartlieb ,  Axel Reithofer ,  Klaus Strohmayer

发明人： Heimo Hartlieb ,  Axel Reithofer ,  Klaus Strohmayer

IPC分类号： G05F1/00

CPC分类号： H02M3/156 ,  H02M2003/1555

摘要： Current regulators and related methods for regulating a current through a load. The current regulator may include, for example, a first circuit configured to determine an amount of current that flows through the load; and a second circuit configured to cause a voltage to be applied across the load, the voltage having a duty cycle that depends on the amount of the current flowing through the load.

摘要翻译： 用于调节通过负载的电流的电流调节器和相关方法。 电流调节器可以包括例如被配置为确定流过负载的电流量的第一电路; 以及第二电路，被配置为使电压施加在负载两端，该电压具有取决于流过负载的电流量的占空比。

公开(公告)号：US07663521B2

公开(公告)日：2010-02-16

申请号：US12051655

申请日：2008-03-19

申请人： Heimo Hartlieb ,  Klaus Strohmayer ,  Michael Hausmann

发明人： Heimo Hartlieb ,  Klaus Strohmayer ,  Michael Hausmann

IPC分类号： H03M1/00

CPC分类号： G05B11/36

摘要： An embodiment of the invention relates to a controller that includes a delta-sigma modulator to produce a one-bit, oversampled signal representing a measured characteristic of a process, and a delta-sigma modulator to produce a one-bit, oversampled signal representing a set-point value for the characteristic. A multiplexer selects a partial sum based on a difference of the oversampled signals to produce a control signal for the process. The controller that produces the control signal for the process can be a PID controller.

摘要翻译： 本发明的一个实施例涉及一种控制器，其包括Δ-Σ调制器以产生表示过程的测量特性的1比特过采样信号，以及Δ-Σ调制器以产生一个1比特的过采样信号， 特征值的设定值。 复用器基于过采样信号的差异选择部分和，以产生用于该过程的控制信号。 产生过程控制信号的控制器可以是PID控制器。

公开(公告)号：US07848126B2

公开(公告)日：2010-12-07

申请号：US11842196

申请日：2007-08-21

申请人： Heimo Hartlieb ,  Axel Reithofer ,  Klaus Strohmayer

发明人： Heimo Hartlieb ,  Axel Reithofer ,  Klaus Strohmayer

IPC分类号： G05F1/565

CPC分类号： H02M3/156 ,  H02M2003/1555

摘要： Current regulators and related method for regulating a current through a load. The current regulator may include, for example, a first circuit configured to determine an amount of current that flows through the load; and a second circuit configured to cause a voltage to be applied across the load, the voltage having a duty cycle that depends on the amount of the current flowing through the load.

摘要翻译： 用于调节通过负载的电流的电流调节器和相关方法。 电流调节器可以包括例如被配置为确定流过负载的电流量的第一电路; 以及第二电路，被配置为使电压施加在负载两端，该电压具有取决于流过负载的电流量的占空比。

公开(公告)号：US20090237282A1

公开(公告)日：2009-09-24

申请号：US12051655

申请日：2008-03-19

申请人： Heimo Hartlieb ,  Klaus Strohmayer ,  Michael Hausmann

发明人： Heimo Hartlieb ,  Klaus Strohmayer ,  Michael Hausmann

IPC分类号： H03M3/00

CPC分类号： G05B11/36

摘要： An embodiment of the invention relates to a controller that includes a delta-sigma modulator to produce a one-bit, oversampled signal representing a measured characteristic of a process, and a delta-sigma modulator to produce a one-bit, oversampled signal representing a set-point value for the characteristic. A multiplexer selects a partial sum based on a difference of the oversampled signals to produce a control signal for the process. The controller that produces the control signal for the process can be a PID controller.

摘要翻译： 本发明的一个实施例涉及一种控制器，其包括Δ-Σ调制器以产生表示过程的测量特性的1比特过采样信号，以及Δ-Σ调制器以产生一个1比特的过采样信号， 特征值的设定值。 复用器基于过采样信号的差异选择部分和，以产生用于该过程的控制信号。 产生过程控制信号的控制器可以是PID控制器。

公开(公告)号：US06965660B2

公开(公告)日：2005-11-15

申请号：US09969269

申请日：2001-09-28

申请人： Klaus Strohmayer

发明人： Klaus Strohmayer

IPC分类号： H03L7/099 ,  H03L7/10 ,  H03L7/199 ,  H03D3/24

CPC分类号： H03L7/199 ,  H03L7/0991 ,  H03L7/10 ,  H03L2207/18 ,  H03L2207/50

摘要： A digital phase-locked loop is provided having a minimal transient recovery time for emitting an output clock signal which is synchronous with a reference clock signal in a normal operating state of the digital phase-locked loop. The phase-locked loop can include a phase detector for identifying a phase deviation between the reference clock signal and a feedback clock signal. Further, the phase-locked loop can include a resettable counter, which generates a digital phase deviation signal corresponding to the identified phase deviation. The phase-locked loop can also include a resettable digital filter for filtering the digital phase deviation signal. Further, the phase-locked loop can include an oscillator circuit for generating the output clock signal as a function of a filtered digital phase deviation signal. The phase-locked loop can also include a resettable feedback frequency divider which divides the output clock signal for generating the feedback clock signal.

摘要翻译： 提供数字锁相环，具有最小的瞬态恢复时间，用于在数字锁相环的正常工作状态下发射与参考时钟信号同步的输出时钟信号。 锁相环可以包括用于识别参考时钟信号和反馈时钟信号之间的相位偏差的相位检测器。 此外，锁相环可以包括可复位计数器，其产生对应于所识别的相位偏差的数字相位偏差信号。 锁相环还可以包括用于滤波数字相位偏差信号的可复位数字滤波器。 此外，锁相环可以包括用于根据滤波的数字相位偏差信号产生输出时钟信号的振荡器电路。 锁相环还可以包括可复位的反馈分频器，其分频输出时钟信号以产生反馈时钟信号。