公开(公告)号：US4797717A

公开(公告)日：1989-01-10

申请号：US039291

申请日：1987-04-17

申请人： Koichiro Ishibashi ,  Osamu Minato ,  Toshiaki Masuhara ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Shoji Hanamura ,  Nobuyuki Moriwaki ,  Shigeru Honjyo ,  Kiyotsugu Ueda

发明人： Koichiro Ishibashi ,  Osamu Minato ,  Toshiaki Masuhara ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Shoji Hanamura ,  Nobuyuki Moriwaki ,  Shigeru Honjyo ,  Kiyotsugu Ueda

IPC分类号： G11C11/403 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/45 ,  H01L29/78 ,  H01L27/02 ,  H01L29/04

CPC分类号： H01L29/456 ,  H01L27/1112 ,  Y10S257/904

摘要： Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

摘要翻译： SRAM中的每个存储单元包括两个驱动器MOS晶体管，两个传输门MOS晶体管和两个负载电阻。 MOS晶体管的栅极电极层由设置在半导体衬底的表面上的第一级导电层形成。 每个存储单元中的两个驱动器MOS晶体管的源极区域共同连接，并且通过第二级导电层进一步连接到地电位点。 每个存储单元中的两个负载电阻由第三级高电阻材料层形成。 第二级导电层由低电阻材料层形成。 因此，两个驱动器MOS晶体管的源极的电阻降低。

公开(公告)号：US4841486A

公开(公告)日：1989-06-20

申请号：US946776

申请日：1986-12-29

申请人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

发明人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

IPC分类号： H01L27/11 ,  G11C7/06 ,  G11C11/416 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/10

CPC分类号： G11C11/419 ,  G11C7/062

摘要： A semiconductor memory device having a memory plane defined by a plurality of memory cells, a decoder line for accessing the memory cells, a common data line on which a signal output from an accessed memory cell is collected, and a sense amplifier for amplifying the signal collected on the common data line. The sense amplifier has an amplifying circuit portion which is composed of a pair of common-collector type bipolar transistors supplied with the signal collected on the common data line as a differential input, and a plurality of MOS transistors for converting a change in current into a change in voltage. Each of the MOS transistors has a lightly-doped drain structure.

摘要翻译： 一种具有由多个存储单元限定的存储器平面的半导体存储器件，用于访问存储器单元的解码器线，从所访问的存储单元输出的信号被收集的公共数据线，以及用于放大该信号的读出放大器 在公共数据线上收集。 读出放大器具有放大电路部分，该放大电路部分由一对公共集电极型双极晶体管构成，该一对公共集电极型双极晶体管被提供有作为差分输入的公共数据线上收集的信号，以及多个MOS晶体管，用于将电流变化转换为 电压变化。 每个MOS晶体管具有轻掺杂漏极结构。

公开(公告)号：US4747082A

公开(公告)日：1988-05-24

申请号：US76174

申请日：1987-07-21

申请人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

发明人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

IPC分类号： G11C11/406 ,  G11C8/00

CPC分类号： G11C11/406

摘要： A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

摘要翻译： 半导体存储器设置有自动刷新装置，包括定时器，刷新计数器和刷新缓冲器，每个形成在安装有异步存储器的半导体芯片上，用于基于生成的基本时钟信号自动执行周期性刷新操作 响应于对刷新计数器的输出的逻辑改变的检测。 自动刷新计数器包括优先于周期性刷新操作执行基于与周期性刷新操作异步的常规地址信号的读操作和写操作之一的装置。

公开(公告)号：US4849801A

公开(公告)日：1989-07-18

申请号：US113381

申请日：1987-10-27

申请人： Shigeru Honjyo ,  Osamu Minato ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara

发明人： Shigeru Honjyo ,  Osamu Minato ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara

IPC分类号： H01L29/94 ,  G11C11/41 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/1112 ,  Y10S257/903

摘要： A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to increasing the capacitance of the storing node of the memory cell. This semiconductor memory device significantly reduces the occurrence of soft errors.

摘要翻译： 提供一种半导体存储器件，其中施加有电源电压或接地电压的电极设置在构成静态存储器件的存储单元的MOS晶体管的漏极和/或栅极上的绝缘层上，从而 增加存储单元的存储节点的电容。 该半导体存储器件显着地减少了软错误的发生。

公开(公告)号：US4785342A

公开(公告)日：1988-11-15

申请号：US8325

申请日：1987-01-29

申请人： Toshiaki Yamanaka ,  Yoshio Sakai ,  Shinpei Iijima ,  Osamu Minato ,  Shigeru Honjyo

发明人： Toshiaki Yamanaka ,  Yoshio Sakai ,  Shinpei Iijima ,  Osamu Minato ,  Shigeru Honjyo

IPC分类号： H01L27/11 ,  G11C11/41 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/102 ,  H01L29/04 ,  H01L29/40 ,  H01L49/02

CPC分类号： H01L27/1025

摘要： A resistance element having a reduced occupied area and a high resistance which may be employed as a load resistor used in, for example, a static memory device. A high-resistance area is formed using a relatively thin film, while an interconnection area is formed using a relatively thick film, and these films are provided in such a manner that the thin film is in contact with the upper side of the thick film (the relatively thick film is a first-level film, and the relatively thin film is a second-level film).

摘要翻译： 具有减小的占用面积和高电阻的电阻元件，其可以用作例如静态存储器件中使用的负载电阻器。 使用相对薄的膜形成高电阻区域，而使用相对厚的膜形成互连区域，并且这些膜以这样的方式设置，使得薄膜与厚膜的上侧接触（ 相对厚的膜是第一级膜，相对薄膜是第二级膜）。