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    Semiconductor integrated circuit device
    4.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5619055A

    公开(公告)日：1997-04-08

    申请号：US429882

    申请日：1995-04-27

    申请人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

    发明人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

    摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.

    摘要翻译： 公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET之上。 存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由不同于导电膜的驱动MISFET组成的栅电极构成。 在具有这种堆叠布置的存储器单元中，每个负载MISFET的源极区域和栅电极被图案化以具有彼此广泛重叠的关系，以形成电容器元件，使得与每个负载MISFET相关联的总体电容的增加 存储单元存储节点被实现，从而减少软错误的发生。 通过p型杂质离子注入到半导体条中的方式来提供跨越各个负载MISFET的源极和栅极的大电容器元件的重叠关系。 添加用于形成负载MISFET的源极区域的离子注入的单独的掩模，然后以与源极区域具有广泛重叠的关系的方式添加其栅电极。

    Semiconductor integrated circuit device
    6.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5700705A

    公开(公告)日：1997-12-23

    申请号：US470452

    申请日：1995-06-06

    申请人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

    发明人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

    IPC分类号： H01L21/8244 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

    摘要： The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type or of n-type and p-type polycrystalline silicon films, respectively, and electrical connections are formed between the drain regions of the first and second p-channel load MISFETs with that of the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. Also, there are formed electrical connections between the polycrystalline silicon gate electrodes of the first and second load MISFETs with that of drain regions of the second and first drive MISFETs, through the poly-Si gate electrodes of the first and second drive MISFETs, in each memory cell of the SRAM, respectively, furthermore.

    摘要翻译： 公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元的制造，其中负载MISFET堆叠在半导体衬底上方和驱动MISFET上方。 每个负载MISFET的制造包括在同一多晶硅膜内形成源极，漏极和沟道区域，以及由不同层导电膜（例如多晶膜）组成的栅电极，而不是驱动MISFET。 具有这种堆叠布置的存储单元的制造有助于其每个负载MISFET的源极（漏极）区域和栅极电极的图案化，以使得彼此之间具有重叠关系，从而增加与每个负载MISFET相关联的有效电容 存储单元存储节点。 驱动和负载MISFET的栅电极分别由n型或n型和p型多晶硅膜形成，并且在第一和第二p沟道负载MISFET的漏极区之间形成电连接 与第一和第二n沟道驱动MISFET的漏极区分别通过分离的多晶硅膜。 此外，通过第一和第二驱动MISFET的多晶硅栅电极，在第一和第二负载MISFET的多晶硅栅电极与第二和第一驱动MISFET的漏极区域之间形成电连接 此外，SRAM的存储单元分别。

    Semiconductor integrated circuit device
    9.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5646423A

    公开(公告)日：1997-07-08

    申请号：US470451

    申请日：1995-06-06

    申请人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

    发明人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/04 ,  H01L31/036

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

    摘要： A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type and p-type polycrystalline silicon films, respectively, and the drain regions of the first and second p-channel load MISFETs are electrically connected to the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. The polycrystalline silicon gate electrodes of the first and second load MISFETs are respectively electrically connected to the drain regions of the second and first drive MISFETs in each memory cell of the SRAM, furthermore.

    摘要翻译： 公开了SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFETS之上。 存储单元的每个负载MISFET由形成在同一多晶硅膜内的源极，漏极和沟道区域以及由与驱动MISFET不同的导电膜构成的栅电极组成。 在具有这种堆叠布置的存储单元中，其每个负载MISFET的源极（漏极）区域和栅电极被图案化以具有彼此重叠的关系，从而增加与每个存储单元存储节点相关联的有效电容 。 驱动和负载MISFET两者的栅电极分别由n型和p型多晶硅膜形成，并且第一和第二p沟道负载MISFET的漏极区域电连接到第一 和第二n沟道驱动MISFET分别通过单独的多晶硅膜。 此外，第一和第二负载MISFET的多晶硅栅电极分别电连接到SRAM的每个存储单元中的第二和第一驱动MISFET的漏极区。

    Semiconductor memory device having flip-flop circuits
    10.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US5132771A

    公开(公告)日：1992-07-21

    申请号：US503928

    申请日：1990-04-04

    申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    IPC分类号： G11C11/412 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

    摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。