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    Data processing apparatus
    1.
    发明授权
    Data processing apparatus 失效
    数据处理装置

    公开(公告)号：US4712175A

    公开(公告)日：1987-12-08

    申请号：US633981

    申请日：1984-07-24

    申请人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

    发明人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

    IPC分类号： G06F17/16 ,  G06F9/38 ,  G06F15/78 ,  G06F15/347 ,  G06F15/16

    CPC分类号： G06F15/8076 ,  G06F9/3885

    摘要： A data processing apparatus comprises a plurality of sub-systems each including at least one arithmetic unit, a plurality of registers, a first selector for receiving vector data and selectively outputting the input data to the registers, and a second selector for receiving the vector data from the registers and selectively outputting the input data to a plurality of output lines. The data output of the arithmetic unit in each sub-system is supplied to the first selector in the same sub-system and the first selector in another sub-system, and the arithmetic unit in each sub-system receives the output data from the second selector in the same sub-system. The data output from the second selector in at least one sub-system is supplied to a main storage unit, and the data output from the main storage unit is supplied to the first selector in at least one sub-system.

    摘要翻译： 数据处理装置包括多个子系统，每个子系统包括至少一个算术单元，多个寄存器，用于接收向量数据的第一选择器，并且将输入数据选择性地输出到寄存器;以及第二选择器，用于接收向量数据 从寄存器中选择性地将输入数据输出到多条输出线。 每个子系统中的算术单元的数据输出被提供给同一子系统中的第一选择器和另一子系统中的第一选择器，并且每个子系统中的算术单元从第二子系统接收输出数据 选择器在同一子系统中。 在至少一个子系统中从第二选择器输出的数据被提供给主存储单元，并且从主存储单元输出的数据在至少一个子系统中提供给第一选择器。

    Vector data processor
    2.
    发明授权
    Vector data processor 失效
    矢量数据处理器

    公开(公告)号：US4651274A

    公开(公告)日：1987-03-17

    申请号：US594301

    申请日：1984-03-28

    申请人： Koichiro Omoda ,  Shigeo Nagashima ,  Shunichi Torii

    发明人： Koichiro Omoda ,  Shigeo Nagashima ,  Shunichi Torii

    IPC分类号： G06F17/16 ,  G06F9/38 ,  G06F15/78 ,  G06F13/00 ,  G06F9/00

    CPC分类号： G06F15/8084 ,  G06F9/3867

    摘要： A vector data processor includes a vector index register for consecutively and sequentially storing indirect address vectors, which may then be consecutively and sequentially read out from the vector index register to form addresses of data, thereby to execute the consecutive reading of the data from a main storage and the consecutive writing thereof into the main storage with an increased processing speed by generating addresses and storing data in overlapping operations.

    摘要翻译： 向量数据处理器包括一个向量索引寄存器，用于连续和顺序地存储间接地址向量，然后可以从向量索引寄存器连续地顺序地读出数据，以形成数据的地址，从而执行从主要的数据的连续读取 通过在重叠操作中生成地址和存储数据，以其增加的处理速度将其连续写入主存储器。

    Data process system including plural storage means each capable of concurrent and intermediate reading and writing of a set of data signals
    3.
    发明授权
    Data process system including plural storage means each capable of concurrent and intermediate reading and writing of a set of data signals 失效
    数据处理系统包括多个存储装置，每个存储装置能够并行和中间读取和写入一组数据信号

    公开(公告)号：US4734850A

    公开(公告)日：1988-03-29

    申请号：US581077

    申请日：1984-02-17

    申请人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

    发明人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

    IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F5/16 ,  G06F12/00 ,  G06F12/06 ,  G06F17/16 ,  G11C7/00 ,  G06F9/18

    CPC分类号： G06F5/16

    摘要： A data processing system having a plurality of FIFO memories and a plurality of ALUs and in which a FIFO memory may be selected to receive a set of data signals from an ALU and at the same time to be selected to provide a set of data signals to another ALU, with the result that the selected FIFO memory performs read and write operations concurrently and intermittently. Also, a set of data signals held by one of the FIFO memories may be transferred to a selected ALU for effecting a logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation by the selected ALU may be transferred to another FIFO memory.

    摘要翻译： 一种具有多个FIFO存储器和多个ALU的数据处理系统，其中可以选择FIFO存储器以从ALU接收一组数据信号，并且同时被选择以提供一组数据信号 另一个ALU，结果是所选择的FIFO存储器同时并间歇地执行读写操作。 此外，由FIFO存储器中的一个保存的一组数据信号可以被传送到所选择的ALU以进行其上的逻辑或算术运算，并且表示其上的逻辑或运算结果的结果的数据信号，以及代表 所选择的ALU的逻辑或算术运算的结果可以被传送到另一个FIFO存储器。

    Vector processor for reordering vector data during transfer from main memory to vector registers
    4.
    发明授权
    Vector processor for reordering vector data during transfer from main memory to vector registers 失效
    向量处理器，用于在从主存储器传送到向量寄存器时重新排列向量数据

    公开(公告)号：US4825361A

    公开(公告)日：1989-04-25

    申请号：US21590

    申请日：1987-03-02

    申请人： Koichiro Omoda ,  Shunichi Torii ,  Shigeo Nagashima ,  Yasuhiro Inagami ,  Takayuki Nakagawa

    发明人： Koichiro Omoda ,  Shunichi Torii ,  Shigeo Nagashima ,  Yasuhiro Inagami ,  Takayuki Nakagawa

    IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F15/347

    CPC分类号： G06F15/8076

    摘要： A vector processor having a vector register made up of elements of l.sub.2 -byte size for storing vector data made up of a plurality of elements read out from a main storage which has a plurality of storage areas and is capable of reading out data of l.sub.1 -byte size beginning from a specified address bound, and adapted to write vector data with an element size of m (l.sub.1 /m is an integer and l.sub.2 is larger or equal to m) into the vector register sequentially, read-out vector data from the vector register for computation by an arithmetic unit, and write the computational result into the vector register, wherein the processor writes elements of vector data read out from the main storage into separatte, specified locations of the vector register in an order required for subsequent operations.

    摘要翻译： 一种矢量处理器，具有由12位字节大小的元素构成的向量寄存器，用于存储由从具有多个存储区域的主存储器读出的多个元素组成的矢量数据，并且能够读出l1- 字节大小从指定的地址限制开始，并适用于顺序地向向量寄存器中写入具有m（l1 / m为整数，l2大于或等于m）的元素大小的向量数据，从 向量寄存器，用于由算术单元计算，并将计算结果写入向量寄存器，其中处理器以从后续操作所需的顺序将从主存储器读出的向量数据的元素写入分离的向量寄存器的指定位置。

    Data storage device
    5.
    发明授权
    Data storage device 失效
    数据存储设备

    公开(公告)号：US4809161A

    公开(公告)日：1989-02-28

    申请号：US799018

    申请日：1985-11-18

    申请人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

    发明人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

    IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F5/16 ,  G06F12/00 ,  G06F12/06 ,  G06F17/16 ,  G11C7/00 ,  G11C19/00

    CPC分类号： G06F5/16

    摘要： A plurality of data bands operable independently from each other is controlled by a control circuit so that a set of received data signals are written into respective storage locations predetermined for respective data signals within respective data banks predetermined for respective data signals, wherein respective storage locations and respective data banks for respective received data signals are predetermined depending upon the arrival numbers of respective received data signals and a predetermined bank order, so that respective storage locations for two data signals received one after another belong to different data banks arranged according to the bank order. The data banks are controlled by the control circuit so that a set of data signals are read out according to the order of receipt of the set of data signals and from a timing before completion of the writing of the set under a condition that each data bank performs only one of write and read operations during a clock period.

    摘要翻译： 由控制电路控制多个可彼此独立操作的数据频带，使得一组接收的数据信号被写入对于相应数据信号预定的相应数据信号的相应存储位置，该各个数据信号预定用于各个数据信号，其中相应的存储位置和 各个接收数据信号的各个数据组根据各个接收数据信号的到达数和预定的存储体顺序被预先确定，使得一个接一个地接收的两个数据信号的各自的存储位置属于根据存储体顺序排列的不同数据库 。 数据组由控制电路控制，使得一组数据信号根据数据信号组的接收顺序以及在每个数据库的条件下从该组的写入完成之前的定时读出 在时钟周期内只执行一次写入和读取操作。

    Pipelined operation unit for vector data
    7.
    发明授权
    Pipelined operation unit for vector data 失效
    用于矢量数据的流水线操作单元

    公开(公告)号：US4525796A

    公开(公告)日：1985-06-25

    申请号：US347720

    申请日：1982-02-10

    申请人： Koichiro Omoda ,  Yasuhiro Inagami ,  Shunichi Torii ,  Shigeo Nagashima

    发明人： Koichiro Omoda ,  Yasuhiro Inagami ,  Shunichi Torii ,  Shigeo Nagashima

    IPC分类号： G06F17/16 ,  G06F7/544 ,  G06F9/38 ,  G06F15/78 ,  G06F7/00

    CPC分类号： G06F15/8053 ,  G06F7/5443 ,  G06F9/3885

    摘要： In an operation unit wherein a series of data is sequentially applied, a predetermined operation is performed in synchronism with the input data in a pipelined manner, and the predetermined operation is applied to an input data and the result of the predetermined operation for a preceding input data. There are provided a plurality of partial operation devices which respectively compute a plurality of different partial data of a result data to be obtained as a result of the predetermined operation, and when one of the partial data is obtained, the one partial data is immediately used for the operation for the subsequent input data. Consequently, the operation for the subsequent input data can be started before the operation for the remainder of the partial data of the preceding input data is completed.

    摘要翻译： 在顺序地应用一系列数据的操作单元中，以流水线方式与输入数据同步地执行预定操作，并且将预定操作应用于输入数据，并将预定操作的结果用于前一个输入 数据。 提供了多个部分操作装置，其分别计算作为预定操作的结果将要获得的结果数据的多个不同部分数据，并且当获得部分数据之一时，立即使用一个部分数据 用于后续输入数据的操作。 因此，在完成前一输入数据的部分数据的其余部分的操作之前，可以开始后续输入数据的操作。

    Data storage device
    8.
    发明授权
    Data storage device 失效
    数据存储设备

    公开(公告)号：US5295252A

    公开(公告)日：1994-03-15

    申请号：US296827

    申请日：1989-01-13

    申请人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

    发明人： Shunichi Torii ,  Shigeo Nagashima ,  Koichiro Omoda

    IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F5/16 ,  G06F12/00 ,  G06F12/06 ,  G06F17/16 ,  G11C7/00

    CPC分类号： G06F5/16

    摘要： A plurality of data banks operable independently from each other is controlled by a control circuit so that a set of received data signals are written into respective storage locations predetermined for respective data signals within respective data banks predetermined for respective data signals, wherein respective storage locations and respective data banks for respective received data signals are predetermined depending upon the arrival numbers of respective received data signals and a predetermined bank order, so that respective storage locations for two data signals received one after another belong to different data banks arranged according to the bank order. The data banks are controlled by the control circuit so that a set of data signals are read out according to the order of receipt of the set of data signals and from a timing before completion of the writing of the set under a condition that each data bank performs only one of write and read operations during a clock period.

    摘要翻译： 由控制电路控制多个彼此独立操作的数据库，使得一组接收到的数据信号被写入对于相应数据信号预定的相应数据信号的相应存储位置中，该各个数据信号预定用于相应的数据信号，其中相应的存储位置和 各个接收数据信号的各个数据组根据各个接收数据信号的到达数和预定的存储体顺序被预先确定，使得一个接一个地接收的两个数据信号的各自的存储位置属于根据存储体顺序排列的不同数据库 。 数据组由控制电路控制，使得一组数据信号根据数据信号组的接收顺序以及在每个数据库的条件下从该组的写入完成之前的定时读出 在时钟周期内只执行一次写入和读取操作。