-
1.发明授权Vector processor for reordering vector data during transfer from main memory to vector registers 失效向量处理器，用于在从主存储器传送到向量寄存器时重新排列向量数据
公开(公告)号：US4825361A
公开(公告)日：1989-04-25
申请号：US21590
申请日：1987-03-02
IPC分类号： G06F17/16 , G06F15/78 , G06F15/347
CPC分类号： G06F15/8076
摘要： A vector processor having a vector register made up of elements of l.sub.2 -byte size for storing vector data made up of a plurality of elements read out from a main storage which has a plurality of storage areas and is capable of reading out data of l.sub.1 -byte size beginning from a specified address bound, and adapted to write vector data with an element size of m (l.sub.1 /m is an integer and l.sub.2 is larger or equal to m) into the vector register sequentially, read-out vector data from the vector register for computation by an arithmetic unit, and write the computational result into the vector register, wherein the processor writes elements of vector data read out from the main storage into separatte, specified locations of the vector register in an order required for subsequent operations.
摘要翻译： 一种矢量处理器，具有由12位字节大小的元素构成的向量寄存器，用于存储由从具有多个存储区域的主存储器读出的多个元素组成的矢量数据，并且能够读出l1- 字节大小从指定的地址限制开始，并适用于顺序地向向量寄存器中写入具有m（l1 / m为整数，l2大于或等于m）的元素大小的向量数据，从 向量寄存器，用于由算术单元计算，并将计算结果写入向量寄存器，其中处理器以从后续操作所需的顺序将从主存储器读出的向量数据的元素写入分离的向量寄存器的指定位置。
-
2.发明授权Data processing system including scalar data processor and vector data processor 失效数据处理系统包括标量数据处理器和矢量数据处理器
公开(公告)号：US4541046A
公开(公告)日：1985-09-10
申请号：US361478
申请日：1982-03-23
CPC分类号： G06F9/3887 , G06F15/8061 , G06F9/30036 , G06F9/3879
摘要： A vector processor comprises a main storage for storing scalar instruction chains and vector instruction chains for executing desired operations, and a scalar processing unit and a vector processing unit for separately fetching the scalar instruction chains and the vector instruction chains, decoding them and executing them so that the scalar processing and the vector processing are carried out in overlap.
摘要翻译： 矢量处理器包括用于存储用于执行期望操作的标量指令链和矢量指令链的主存储器，以及用于分别取出标量指令链和向量指令链的标量处理单元和向量处理单元，对它们进行解码并执行它们 标量处理和向量处理以重叠的方式执行。
-
公开(公告)号：US4525796A
公开(公告)日：1985-06-25
申请号：US347720
申请日：1982-02-10
CPC分类号： G06F15/8053 , G06F7/5443 , G06F9/3885
摘要： In an operation unit wherein a series of data is sequentially applied, a predetermined operation is performed in synchronism with the input data in a pipelined manner, and the predetermined operation is applied to an input data and the result of the predetermined operation for a preceding input data. There are provided a plurality of partial operation devices which respectively compute a plurality of different partial data of a result data to be obtained as a result of the predetermined operation, and when one of the partial data is obtained, the one partial data is immediately used for the operation for the subsequent input data. Consequently, the operation for the subsequent input data can be started before the operation for the remainder of the partial data of the preceding input data is completed.
摘要翻译： 在顺序地应用一系列数据的操作单元中，以流水线方式与输入数据同步地执行预定操作，并且将预定操作应用于输入数据，并将预定操作的结果用于前一个输入 数据。 提供了多个部分操作装置，其分别计算作为预定操作的结果将要获得的结果数据的多个不同部分数据，并且当获得部分数据之一时，立即使用一个部分数据 用于后续输入数据的操作。 因此，在完成前一输入数据的部分数据的其余部分的操作之前，可以开始后续输入数据的操作。
-
公开(公告)号：US4488247A
公开(公告)日：1984-12-11
申请号：US366325
申请日：1982-04-07
CPC分类号： G06F7/535 , G06F2207/3884 , G06F2207/5355 , G06F7/49942
摘要： An approximate quotient-correcting circuit wherein an approximate quotient Q.sub.H, a divisor D, and the least significant bit of the fraction part of a dividend N are read out; the approximate quotient Q.sub.H and the divisor D are multiplied; it is decided whether the lower m digits of Q.sub.H .times.D are not all `0` and whether the m-th significant bit of Q.sub.H .times.D is coincident with the m-th significant bit of N; and when the result of the decision is positive, Q.sub.H -2.sup.-m is provided as a quotient.
摘要翻译： 一个近似商校正电路，其中读出一个近似商QH，一个除数D和一个除数N的分数部分的最低有效位; 乘数近似商QH和除数D; 确定QHxD的较低m位不是全为“0”，QHxD的第m个有效位是否与N的第m个有效位一致; 当决定结果为正时，提供QH-2-m作为商。
-
5.发明授权Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit 失效矢量处理器，带矢量缓冲存储器，用于在矢量存储和操作单元之间读取或写入矢量数据
公开(公告)号：US4910667A
公开(公告)日：1990-03-20
申请号：US184788
申请日：1988-04-22
申请人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
发明人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
CPC分类号： G06F15/8053
摘要： In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided. The vector buffer storage control checks if the identification information of the vector data designated by a vector data fetch instruction for the main storage is in the indentification storage, and if it is in the identification storage, it fetches the vector data from the buffer storage and transfers it to the vector register, and if it is not in the identification storage, it instructs to fetch the vector data from the main storage, transfers the vector data fetched from the main storage to the vector register and stores it into the buffer storage.
摘要翻译： 在具有向量寄存器的向量处理器中，用于临时存储向量数据的向量缓冲存储器比向主存储器靠近向量寄存器布置，并且向量缓冲器存储控制包括用于存储存储在 提供缓冲存储器的存储位置和用于检查矢量数据识别信息是否在识别存储器中的检查电路。 向量缓冲存储控制检查由主存储器的矢量数据获取指令指定的矢量数据的识别信息是否在识别存储器中，并且如果它在识别存储器中，则从缓冲存储器中取出向量数据， 将其传送到向量寄存器，如果不在识别存储器中，则指示从主存储器获取向量数据，将从主存储器获取的向量数据传送到向量寄存器，并将其存储到缓冲存储器中。
-
6.发明授权Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions 失效能够平行执行指令并保留执行状态顺序的矢量处理器重新启动中断的执行
公开(公告)号：US4782441A
公开(公告)日：1988-11-01
申请号：US872396
申请日：1986-06-10
CPC分类号： G06F15/8053
摘要： In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.
摘要翻译： 在其中通过一个指令处理多个数据并且多个指令并行处理的诸如矢量处理器的处理器中，提供装置，用于在当前执行的程序的中断期间存储在 正在执行的指令的程序中出现的概念顺序，以及处理的数据组的顺序计数。 存储的信息用于在适当的点重新启动中断的程序的执行。
-
7.发明授权Vector data refer circuit with a preceding paging control for a vector processor apparatus therefor 失效矢量数据参考电路与前面的用于其的矢量处理器装置的寻呼控制
公开(公告)号：US4768146A
公开(公告)日：1988-08-30
申请号：US859373
申请日：1986-05-05
CPC分类号： G06F15/8061 , G06F12/1027
摘要： A unit operative in concurrence with a vector processing for beforehand sequentially generating page addresses containing vector data to be referred to thereafter and a unit for achieving a processing to determine whether or not a page fault occurs in a page in an address translation and responsive to an occurrence of a page fault in a page for executing processing to beforehand transfer the page to a main storage are provided. Even if a vector element existing in the page becomes necessary in the vector processing after the operation described above, another paging processing is not necessary because the page exists in the main storage.
摘要翻译： 一种与矢量处理一致的单元，用于预先顺序地生成包含以后要参考的矢量数据的页地址，以及用于实现处理的单元，以确定在地址转换中的页面中是否发生页面错误，并响应于 提供了用于执行预先将页面传送到主存储器的处理的页面中的页面错误的发生。 即使在上述操作之后的矢量处理中存在页面中的矢量元素也是必要的，因为页面存在于主存储器中，所以不需要另外的寻呼处理。
-
公开(公告)号：US4712175A
公开(公告)日：1987-12-08
申请号：US633981
申请日：1984-07-24
申请人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
发明人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
IPC分类号： G06F17/16 , G06F9/38 , G06F15/78 , G06F15/347 , G06F15/16
CPC分类号： G06F15/8076 , G06F9/3885
摘要： A data processing apparatus comprises a plurality of sub-systems each including at least one arithmetic unit, a plurality of registers, a first selector for receiving vector data and selectively outputting the input data to the registers, and a second selector for receiving the vector data from the registers and selectively outputting the input data to a plurality of output lines. The data output of the arithmetic unit in each sub-system is supplied to the first selector in the same sub-system and the first selector in another sub-system, and the arithmetic unit in each sub-system receives the output data from the second selector in the same sub-system. The data output from the second selector in at least one sub-system is supplied to a main storage unit, and the data output from the main storage unit is supplied to the first selector in at least one sub-system.
摘要翻译： 数据处理装置包括多个子系统，每个子系统包括至少一个算术单元，多个寄存器，用于接收向量数据的第一选择器，并且将输入数据选择性地输出到寄存器;以及第二选择器，用于接收向量数据 从寄存器中选择性地将输入数据输出到多条输出线。 每个子系统中的算术单元的数据输出被提供给同一子系统中的第一选择器和另一子系统中的第一选择器，并且每个子系统中的算术单元从第二子系统接收输出数据 选择器在同一子系统中。 在至少一个子系统中从第二选择器输出的数据被提供给主存储单元，并且从主存储单元输出的数据在至少一个子系统中提供给第一选择器。
-
公开(公告)号：US4651274A
公开(公告)日：1987-03-17
申请号：US594301
申请日：1984-03-28
申请人： Koichiro Omoda , Shigeo Nagashima , Shunichi Torii
发明人： Koichiro Omoda , Shigeo Nagashima , Shunichi Torii
CPC分类号： G06F15/8084 , G06F9/3867
摘要： A vector data processor includes a vector index register for consecutively and sequentially storing indirect address vectors, which may then be consecutively and sequentially read out from the vector index register to form addresses of data, thereby to execute the consecutive reading of the data from a main storage and the consecutive writing thereof into the main storage with an increased processing speed by generating addresses and storing data in overlapping operations.
摘要翻译： 向量数据处理器包括一个向量索引寄存器，用于连续和顺序地存储间接地址向量，然后可以从向量索引寄存器连续地顺序地读出数据，以形成数据的地址，从而执行从主要的数据的连续读取 通过在重叠操作中生成地址和存储数据，以其增加的处理速度将其连续写入主存储器。
-
10.发明授权Data process system including plural storage means each capable of concurrent and intermediate reading and writing of a set of data signals 失效数据处理系统包括多个存储装置，每个存储装置能够并行和中间读取和写入一组数据信号
公开(公告)号：US4734850A
公开(公告)日：1988-03-29
申请号：US581077
申请日：1984-02-17
申请人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
发明人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
CPC分类号： G06F5/16
摘要： A data processing system having a plurality of FIFO memories and a plurality of ALUs and in which a FIFO memory may be selected to receive a set of data signals from an ALU and at the same time to be selected to provide a set of data signals to another ALU, with the result that the selected FIFO memory performs read and write operations concurrently and intermittently. Also, a set of data signals held by one of the FIFO memories may be transferred to a selected ALU for effecting a logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation by the selected ALU may be transferred to another FIFO memory.
摘要翻译： 一种具有多个FIFO存储器和多个ALU的数据处理系统，其中可以选择FIFO存储器以从ALU接收一组数据信号，并且同时被选择以提供一组数据信号 另一个ALU，结果是所选择的FIFO存储器同时并间歇地执行读写操作。 此外，由FIFO存储器中的一个保存的一组数据信号可以被传送到所选择的ALU以进行其上的逻辑或算术运算，并且表示其上的逻辑或运算结果的结果的数据信号，以及代表 所选择的ALU的逻辑或算术运算的结果可以被传送到另一个FIFO存储器。
-
-
-
-
-
-
-
-
-
搜索结果
41 条记录 (耗时 0.024 秒)
