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1.发明公开公开(公告)号：US20240340020A1
公开(公告)日：2024-10-10
申请号：US18471437
申请日：2023-09-21
Inventor： Chulwoo KIM , Soohoo PARK , Yohan CHOI , Chang Joo KIM
CPC classification number: H03M1/462 , H03M1/1245
Abstract: Disclosed is an analog-to-digital conversion device. The analog-to-digital conversion device includes a signal generating unit that generates a plurality of comparison voltages based on an analog input voltage and generates a plurality of comparison results of the plurality of comparison voltages based on a sampling period, a calculation unit that skips a comparison result generated by a comparison voltage having a smallest difference between the analog input voltages among the plurality of comparison voltages from the plurality of comparison results and generates an end of comparison based on a remaining plurality of comparison results, and a SAR logic unit that generates a digital signal corresponding to the end of comparison and stores information for each bit of the digital signal.
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公开(公告)号：US20220197443A1
公开(公告)日：2022-06-23
申请号：US17168387
申请日：2021-02-05
Inventor： Chulwoo KIM , Soonsung AHN
IPC: G06F3/044 , G06F3/0354 , G06F3/046 , G06F3/041
Abstract: Disclosed is an electronic device, which includes a plurality of driving coils that are sequentially arranged in a first direction in a plan view, a plurality of sensing electrodes that are spaced and insulated from the plurality of driving coils and are sequentially arranged in a second direction orthogonal or pseudo-orthogonal to the first direction in a plan view, and a processor that is electrically connected with the plurality of driving coils and the plurality of sensing electrodes. At least one of the plurality of sensing electrodes is electrically coupled with a stylus excited by a magnetic field generated by the plurality of driving coils. The processor applies a driving signal to the plurality of driving coils, receives a response signal to the driving signal from the plurality of sensing electrodes, and identifies a contact location of the stylus based on the response signal.
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公开(公告)号：US20200371643A1
公开(公告)日：2020-11-26
申请号：US16776688
申请日：2020-01-30
Inventor： Chulwoo KIM
Abstract: A display device includes a first touch panel on which a first touch sensing unit including a plurality of coils is disposed, a second touch panel on which a second touch sensing unit including a plurality of sensing nodes coupled to the plurality of coils in a coupling manner with a one-to-one correspondence, and a display panel disposed between the first and second touch panels and displays an image, and the plurality of sensing nodes is formed in a divided structure grouped into first and second node groups based on a touch event detected by the first touch sensing unit.
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公开(公告)号：US20190386676A1
公开(公告)日：2019-12-19
申请号：US16242508
申请日：2019-01-08
Inventor： Chulwoo KIM , Chaekang LIM
IPC: H03M3/00
Abstract: A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.
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公开(公告)号：US20250088394A1
公开(公告)日：2025-03-13
申请号：US18827131
申请日：2024-09-06
Inventor： Chulwoo KIM , Youngwook KWON , Jincheol SIM , Seung-Woo PARK , Seongcheol KIM
Abstract: The transmitter includes a driver that is connected to an output node and drives the output node with a pulse amplitude modulation-4 (PAM-4) signal having four levels of a most significant bit (MSB) and a least significant bit (LSB), and an equalizer that is connected to the output node and compensates for attenuation of the PAM-4 signal based on a first operating voltage, wherein the equalizer compensates for the attenuation based on applying a second operating voltage having a level greater than a level of the first operating voltage to the output node when a transition from a first level to a second level among the four levels is a rising transition, and compensates for the attenuation based on forming a path for extracting an equalizing current from the output node when the transition from the first level to the second level is a falling transition.
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Patent Agency Ranking
公开(公告)号：US20220209761A1
公开(公告)日：2022-06-30
申请号：US17517493
申请日：2021-11-02
Inventor： Minseop LEE , Hyunsu PARK , Jincheol SIM , Chulwoo KIM
Abstract: A duty cycle correction circuit includes a first duty cycle detecting circuit configured to detect a duty cycle of a clock signal with a first resolution; a reference clock generating circuit configured to generate a reference clock signal by adjusting a phase of the clock signal; a second duty cycle detecting circuit configured to detect a duty cycle of the clock signal with a second resolution according to the reference clock signal and the clock signal, the second resolution being finer than the first resolution; a first duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more first control signals output from the first duty cycle detecting circuit; and a second duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more second control signals output from the second duty cycle detecting circuit.
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公开(公告)号：US20200007362A1
公开(公告)日：2020-01-02
申请号：US16454307
申请日：2019-06-27
Inventor： Chulwoo KIM , Hyunsu PARK , Jin Cheol SIM
IPC: H04L25/49
Abstract: According to an embodiment of the inventive concept, a device for PAM-3 signaling includes an encoder selecting one of first to ninth transitions in first and second unit intervals that are successive and mapping data of three bits by using a remaining eight transitions other than the one selected among the first to ninth transitions, and an output driver receiving an output signal of the encoder via an input and generating a multi-level signal having an output voltage of first to third levels. The data of three bits is transmitted to a receiver terminal through the multi-level signal having the output voltage of the first to third levels during the first and second unit intervals that are successive. The device for PAM-3 signaling according to an embodiment of the inventive concept may transmit three bits during two unit intervals and may allow a receiver terminal to detect a windowing phenomenon.
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公开(公告)号：US20230421160A1
公开(公告)日：2023-12-28
申请号：US18081027
申请日：2022-12-14
Inventor： Chulwoo KIM , Seung-Woo PARK , Yoon-Jae CHOI , Jin-Cheol SIM
IPC: H03L7/08 , H03L7/097 , H03K3/0233
CPC classification number: H03L7/0807 , H03L7/097 , H03K3/02332
Abstract: Disclosed in a PAM-4 receiver using pattern-based clock and data recovery circuitry, which includes an analog front end that receives an external signal and recovers channel loss to output a refined PAM-4 signal, a comparison unit that receives the PAM-4 signal and compares the PAM-4 signal with a reference voltage to generate a recovery signal, and a recovery unit that receives the recovery signal and recovers data and a clock. The analog front end includes an equalizer that matches amplitudes of all frequency components of the external signal and an amplifier that amplifies an output signal of the equalizer.
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9.发明公开公开(公告)号：US20240356648A1
公开(公告)日：2024-10-24
申请号：US18583011
申请日：2024-02-21
Inventor： Chulwoo KIM , Seongcheol KIM , Jincheol SIM , Youngwook KWON , Junseob SO
IPC: H04B10/40 , H04B10/524
CPC classification number: H04B10/40 , H04B10/524
Abstract: Disclosed are a PAM-4 transceiver for capacitive-driven channels capable of canceling crosstalk and an operation method thereof. The PAM-4 transceiver includes a first channel that transmits and receives a PAM-4 signal generated based on a first input signal through a coupling capacitor disposed at a transmitting stage, and a second channel and a third channel disposed adjacent to the first channel, and the first channel includes a converter that receives a second input signal of the second channel and a third input signal of the third channel, and a cancellation circuit connected to the converter and that cancels a crosstalk occurring in the first channel due to the second input signal and the third input signal, and the cancellation circuit outputs a compensation signal corresponding to the crosstalk based on the second input signal and the third input signal.
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公开(公告)号：US20240178857A1
公开(公告)日：2024-05-30
申请号：US18335572
申请日：2023-06-15
Inventor： Jihwan HYUN , Chulwoo KIM , Sooho PARK , Junghwan CHOI
CPC classification number: H03M1/38 , H03M1/1245
Abstract: In analog-to-digital conversion, a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuit configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.
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