公开(公告)号：US08041899B2

公开(公告)日：2011-10-18

申请号：US12181701

申请日：2008-07-29

申请人： Kostantin Godin ,  Roman Landa ,  Itay Peled ,  Yakov Tokar ,  Ziv Zamsky

发明人： Kostantin Godin ,  Roman Landa ,  Itay Peled ,  Yakov Tokar ,  Ziv Zamsky

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0859 ,  G06F12/0879

摘要： A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.

摘要翻译： 一种写回分配系统，包括：（i）存储请求电路; （ii）适于生成包括信息单元和信息单元地址的存储请求的处理器; 和（iii）高速缓存模块，连接到存储请求电路和高级存储器单元。 单个缓存模块线包括多个段，每个段适于存储单个信息单元。 通过生成包括多个段提取操作的获取突发，从高级存储器单元检索高速缓存模块行的内容。 存储请求电路包括窥探器和控制器。 窥探者检测在获取突发期间被取出的高速缓存行的高速缓存段的地址的一部分。 如果缓存段的地址部分与信息单元地址的相应部分匹配，则控制器适于从高速缓存模块请求在完成获取突发之前接收信息单元。

公开(公告)号：US20100030974A1

公开(公告)日：2010-02-04

申请号：US12181701

申请日：2008-07-29

申请人： Kostantin Godin ,  Roman Landa ,  Itay Peled ,  Yakov Tokar ,  Ziv Zamsky

发明人： Kostantin Godin ,  Roman Landa ,  Itay Peled ,  Yakov Tokar ,  Ziv Zamsky

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0859 ,  G06F12/0879

摘要： A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.

摘要翻译： 一种写回分配系统，包括：（i）存储请求电路; （ii）适于生成包括信息单元和信息单元地址的存储请求的处理器; 和（iii）高速缓存模块，连接到存储请求电路和高级存储器单元。 单个缓存模块线包括多个段，每个段适于存储单个信息单元。 通过生成包括多个段提取操作的获取突发，从高级存储器单元检索高速缓存模块行的内容。 存储请求电路包括窥探器和控制器。 侦听器检测在获取突发期间被取出的高速缓存行的高速缓存段的地址的一部分。 如果缓存段的地址部分与信息单元地址的相应部分匹配，则控制器适于从高速缓存模块请求在完成获取突发之前接收信息单元。

公开(公告)号：US20110040912A1

公开(公告)日：2011-02-17

申请号：US11575003

申请日：2004-09-10

申请人： Kostantin Godin ,  Moshe Anschel ,  Jacob Efrat ,  Itay Peled ,  Reuven Badash ,  Asher Bastaker ,  Dvir Rune Peleg ,  Ziv Zamsky

发明人： Kostantin Godin ,  Moshe Anschel ,  Jacob Efrat ,  Itay Peled ,  Reuven Badash ,  Asher Bastaker ,  Dvir Rune Peleg ,  Ziv Zamsky

IPC分类号： G06F13/40 ,  G06F13/36

CPC分类号： G06F13/4013 ,  G06F13/4018

摘要： Apparatus and method for bus matching. The method includes: receiving data transfer characteristics at a first endian mode and at a second endian mode; determining a connectivity of multiple devices to an interfacing bus in response to the data transfer characteristics and in response to a relationship between a width of the interfacing bus and a width of each device interface; wherein at least one device interface is connected in parallel to multiple interfacing bus portions; and configuring a control logic such as to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to the connectivity. The apparatus includes: an interfacing bus characterized by an interfacing bus width; a master device, connected to the interfacing bus, whereas the master device includes a master device interface; multiple slave devices, each slave device connected to the interfacing bus and includes a slave device interface; wherein at least one slave device interface is connected in parallel to multiple interfacing bus portions; and control logic, connected to the interfacing bus and to the master device, the control logic is adapted to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to a connectivity of the multiple slave devices to the interfacing bus; whereas said connectivity is responsive to data transfer characteristics and is responsive to relationships between a width of the interfacing bus and a width of each device interface.

摘要翻译： 总线匹配的装置和方法。 该方法包括：在第一端模式和第二端模式下接收数据传输特性; 响应于数据传输特性和响应于接口总线的宽度与每个设备接口的宽度之间的关系，确定多个设备到接口总线的连接性; 其中至少一个设备接口并联连接到多个接口总线部分; 以及配置控制逻辑，例如提供表示在接口总线上传送数据的控制信号; 而控制逻辑被配置为响应于连接。 该装置包括：接口总线，其特征在于接口总线宽度; 主设备，连接到接口总线，而主设备包括主设备接口; 多个从设备，每个从设备连接到接口总线并且包括从设备接口; 其中至少一个从设备接口并联连接到多个接口总线部分; 以及连接到接口总线和主设备的控制逻辑，控制逻辑适于提供表示通过接口总线传送数据的控制信号; 而控制逻辑被配置为响应于多个从设备到接口总线的连接; 而所述连接性响应于数据传输特性，并且响应于接口总线的宽度与每个设备接口的宽度之间的关系。

公开(公告)号：US20150149446A1

公开(公告)日：2015-05-28

申请号：US14415971

申请日：2012-07-27

申请人： Ziv Zamsky ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled

发明人： Ziv Zamsky ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled

IPC分类号： G06F17/30

CPC分类号： G06F16/248 ,  G06F12/10

摘要： Circuitry for a computing system includes a memory arrangement having at least one memory management unit and at least one processor. The at least one processor is arranged to issue a memory query to the memory management unit. The memory management unit is arranged to provide a query result in response to the memory query directly to the processor via a data connection.

摘要翻译： 用于计算系统的电路包括具有至少一个存储器管理单元和至少一个处理器的存储器装置。 所述至少一个处理器被布置成向存储器管理单元发出存储器查询。 存储器管理单元被布置成通过数据连接将响应于存储器查询的查询结果直接提供给处理器。

公开(公告)号：US08117400B2

公开(公告)日：2012-02-14

申请号：US12446413

申请日：2006-10-20

申请人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

发明人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

IPC分类号： G06F12/00

CPC分类号： G06F12/0859 ,  G06F9/3834 ,  G06F12/0862

摘要： A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.

摘要翻译： 一种用于获取信息单元的设备和方法，所述方法包括：通过所述信息单元的可高速缓存操作来接收执行写入的请求; 从数据中取出取出单元，其中取出单元连接到高速缓存模块和高级存储单元; 当所述提取单元为空时，确定所述高速缓存模块是否存储所述信息单元的旧版本; 以及响应于所述确定而响应于所述高速缓存模块选择性地将所述信息单元写入所述高速缓存模块。

公开(公告)号：US20100325366A1

公开(公告)日：2010-12-23

申请号：US12446413

申请日：2006-10-20

申请人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

发明人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

IPC分类号： G06F12/08

CPC分类号： G06F12/0859 ,  G06F9/3834 ,  G06F12/0862

摘要： A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.

摘要翻译： 一种用于获取信息单元的设备和方法，所述方法包括：通过所述信息单元的可高速缓存操作来接收执行写入的请求; 从数据中取出取出单元，其中取出单元连接到高速缓存模块和高级存储单元; 当所述提取单元为空时，确定所述高速缓存模块是否存储所述信息单元的旧版本; 以及响应于所述确定而响应于所述高速缓存模块选择性地将所述信息单元写入所述高速缓存模块。

公开(公告)号：US07620760B2

公开(公告)日：2009-11-17

申请号：US11815189

申请日：2005-02-07

申请人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Leonid Rabinovich ,  Noam Sivan ,  Eitan Zmora ,  Ziv Zamsky

发明人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Leonid Rabinovich ,  Noam Sivan ,  Eitan Zmora ,  Ziv Zamsky

IPC分类号： G06F13/36

CPC分类号： H03K19/0008

摘要： A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit access logics associated with multiple circuits; wherein each circuit access logic is adapted to: (i) provide to the first logic, a circuit write value during a circuit writing period and during an idle period that follows the circuit writing period and ends when another circuit is allowed to write; and (ii) provide a default value when another circuit is allowed to write; and wherein the first logic is adapted to alter a state of the first bus in response to a change between two consecutive circuit write values.

摘要翻译： 一种装置，包括：连接在第一逻辑和第一电路之间的第一总线; 连接在第一逻辑和与多个电路相关联的多个非高阻抗电路访问逻辑之间的一组第二总线; 其中每个电路访问逻辑适于：（i）在电路写入周期期间和在电路写入周期之后的空闲周期期间向第一逻辑提供电路写入值，并且当允许另一个电路写入时结束; 和（ii）当允许另一个电路写入时提供默认值; 并且其中所述第一逻辑适于响应于两个连续电路写入值之间的变化而改变所述第一总线的状态。

公开(公告)号：US20060069877A1

公开(公告)日：2006-03-30

申请号：US10955220

申请日：2004-09-30

申请人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Zvika Rozenshein ,  Ziv Zamsky

发明人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Zvika Rozenshein ,  Ziv Zamsky

IPC分类号： G06F12/00

CPC分类号： G06F12/0859 ,  G06F12/0862 ,  G06F12/0879 ,  G06F13/28

摘要： Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.

摘要翻译： 用于向高速缓存模块提供信息的设备和方法包括：（i）连接到高速缓存模块的至少一个处理器，用于发起从缓存模块检索第一和第二数据的第一和第二请求 单元; （ii）适于接收请求并确定第一和第二数据单元是否是强制性数据单元的逻辑; 连接到所述高速缓存模块的控制器，适于在所述单次提取突发期间检索到的存储器空间包括所述第一和第二强制性数据单元时启动单个提取突发，并且如果存储器空间 在单个提取突发期间可检索不包括第一和第二强制数据单元。

公开(公告)号：US07434009B2

公开(公告)日：2008-10-07

申请号：US10955220

申请日：2004-09-30

申请人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Zvika Rozenshein ,  Ziv Zamsky

发明人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Zvika Rozenshein ,  Ziv Zamsky

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0859 ,  G06F12/0862 ,  G06F12/0879 ,  G06F13/28

摘要： Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.

摘要翻译： 用于向高速缓存模块提供信息的设备和方法包括：（i）连接到高速缓存模块的至少一个处理器，用于发起从缓存模块检索第一和第二数据的第一和第二请求 单元; （ii）适于接收请求并确定第一和第二数据单元是否是强制性数据单元的逻辑; 连接到所述高速缓存模块的控制器，适于在所述单次提取突发期间检索到的存储器空间包括所述第一和第二强制性数据单元时启动单个提取突发，并且如果存储器空间 在单个提取突发期间可检索不包括第一和第二强制数据单元。

公开(公告)号：US20080140894A1

公开(公告)日：2008-06-12

申请号：US11815189

申请日：2005-02-07

申请人： Kostantin Godin ,  Mosche Anschel ,  Yacov Efrat ,  Leonid Rabinovich ,  Noam Sivan ,  Eitan Zmora ,  Ziv Zamsky

发明人： Kostantin Godin ,  Mosche Anschel ,  Yacov Efrat ,  Leonid Rabinovich ,  Noam Sivan ,  Eitan Zmora ,  Ziv Zamsky

IPC分类号： G06F13/364

CPC分类号： H03K19/0008

摘要： A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit access logics associated with multiple circuits; wherein each circuit access logic is adapted to: (i) provide to the first logic, a circuit write value during a circuit writing period and during an idle period that follows the circuit writing period and ends when another circuit is allowed to write; and (ii) provide a default value when another circuit is allowed to write; and wherein the first logic is adapted to alter a state of the first bus in response to a change between two consecutive circuit write values.

摘要翻译： 一种装置，包括：连接在第一逻辑和第一电路之间的第一总线; 连接在第一逻辑和与多个电路相关联的多个非高阻抗电路访问逻辑之间的一组第二总线; 其中每个电路访问逻辑适于：（i）在电路写入周期期间和在电路写入周期之后的空闲周期期间向第一逻辑提供电路写入值，并且当允许另一个电路写入时结束; 和（ii）当允许另一个电路写入时提供默认值; 并且其中所述第一逻辑适于响应于两个连续电路写入值之间的变化而改变所述第一总线的状态。