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公开(公告)号：US06704019B2
公开(公告)日：2004-03-09
申请号：US10123136
申请日：2002-04-17
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G09G539
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US5706034A
公开(公告)日：1998-01-06
申请号：US358988
申请日：1994-12-19
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
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公开(公告)号：US20060203000A1
公开(公告)日：2006-09-14
申请号：US11365493
申请日：2006-03-02
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G09G5/39
摘要： A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
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公开(公告)号：US07019751B2
公开(公告)日：2006-03-28
申请号：US10636769
申请日：2003-08-08
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G09G5/39
摘要： A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，并且缓冲装置用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US5940087A
公开(公告)日：1999-08-17
申请号：US739457
申请日：1996-10-29
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
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公开(公告)号：US06377267B1
公开(公告)日：2002-04-23
申请号：US09593496
申请日：2000-06-14
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G06F1300
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US06222563B1
公开(公告)日：2001-04-24
申请号：US09327355
申请日：1999-06-08
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G06F15167
摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
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公开(公告)号：US07602389B2
公开(公告)日：2009-10-13
申请号：US11365493
申请日：2006-03-02
申请人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
发明人： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC分类号： G06T15/30
摘要： A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
摘要翻译： 一种数据处理系统，包括：存储器控制器; 以及连接到所述存储器控制器的存储器; 其中所述存储器控制器包括一个渲染电路，从而根据在CPU中处理程序后提供的图形数据执行一个生成显示数据的渲染命令，并将所述显示数据存储在所述存储器中。
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公开(公告)号：US5581796A
公开(公告)日：1996-12-03
申请号：US164776
申请日：1993-12-10
申请人： Kazuyoshi Koga , Ryo Fujita , Koyo Katsura , Yasushi Fukunaga , Hideyuki Hara
发明人： Kazuyoshi Koga , Ryo Fujita , Koyo Katsura , Yasushi Fukunaga , Hideyuki Hara
摘要： In a case where a graphic image segment of which positional information is defined in a world coordinate system and of which size information is defined in a device coordinate system is developed to be displayed on a multi-window screen, the development processing performance is improved in peripheral portions of the window. A rectangular development area (first development area) associated with the window is expanded with consideration of a size information of a graphic segment so as to obtain a second development area. The second development area is compared with a rectangular area (an existence area) circumscribing a graphic image represented only with positional information of the graphic segment. As a result, whether or not the graphic segment is to be developed is determined. The first development area is reduced with consideration of size information of the graphic segment to produce a third development area. The third development area is compared with the existence area to decide whether or not the clipping operation is necessary for the graphic segment.
摘要翻译： 在世界坐标系中定义哪个位置信息的图形图像段并且在设备坐标系中定义尺寸信息的情况下，显示在多窗口屏幕上，显影处理性能得到改善 窗口的周边部分。 考虑到图形段的尺寸信息来扩展与窗口相关联的矩形显影区域（第一显影区域），以获得第二显影区域。 将第二开发区域与限定仅由图形段的位置信息表示的图形图像的矩形区域（存在区域）进行比较。 结果，确定图形片段是否被开发。 考虑到图形部分的尺寸信息，第一个开发区域减少，以产生第三个开发区域。 将第三开发区域与存在区域进行比较，以确定剪切操作是否对于图形段是必需的。
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公开(公告)号：US06266072B1
公开(公告)日：2001-07-24
申请号：US08930674
申请日：1997-10-03
申请人： Kazuyoshi Koga , Ryo Fujita , Koyo Katsura , Katsunori Suzuki , Toshiyuki Kuwana
发明人： Kazuyoshi Koga , Ryo Fujita , Koyo Katsura , Katsunori Suzuki , Toshiyuki Kuwana
IPC分类号： G06F1580
CPC分类号： G06T15/503 , G06T11/00
摘要： A graphics system which accelerates generation of pixels including transparent objects by simply adding more rendering devices. The system has composition means and a plurality of rendering devices each comprising a geometric processor, a rendering processor and a frame memory that holds color, depth and weight data in a screen bit map format. Given a plurality of sets of color, depth and weight data about any one pixel position from the frame memories, the composition means first compares the depth data, and multiplies successively the weight and color data starting with those corresponding to the depth data closest to the foreground, thereby generating new pixel data. The system thus permits merging of transparent objects.
摘要翻译： 一种图形系统，通过简单地添加更多的渲染设备来加速像素的生成，包括透明对象。 该系统具有组合装置和多个渲染装置，每个渲染装置包括几何处理器，渲染处理器和以屏幕位图格式保存颜色，深度和重量数据的帧存储器。 给定关于来自帧存储器的任何一个像素位置的多组颜色，深度和重量数据，合成装置首先比较深度数据，并且从与最接近 前景，从而生成新的像素数据。 因此，该系统允许透明对象的合并。
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