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公开(公告)号：US20200310872A1
公开(公告)日：2020-10-01
申请号：US16367581
申请日：2019-03-28
申请人： Krishnamurthy Jambur Sathyanarayana , Robert Valentine , Alexander Gendler , Shmuel Zobel , Gavri Berger , Ian M. Steiner , Nikhil Gupta , Eyal Hadas , Edo Hachamo , Sumesh Subramanian
发明人： Krishnamurthy Jambur Sathyanarayana , Robert Valentine , Alexander Gendler , Shmuel Zobel , Gavri Berger , Ian M. Steiner , Nikhil Gupta , Eyal Hadas , Edo Hachamo , Sumesh Subramanian
IPC分类号： G06F9/48 , G06F9/38 , G06F9/30 , G06F9/4401
摘要： In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.
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公开(公告)号：US10474463B2
公开(公告)日：2019-11-12
申请号：US13997006
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
摘要： An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location.
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公开(公告)号：US10209986B2
公开(公告)日：2019-02-19
申请号：US13976792
申请日：2011-12-22
申请人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
发明人： Jesus Corbal San Adrian , Cristina S. Anderson , Robert Valentine , Bret Toll , Amit Gradstein , Simon Rubanovich , Benny Eitan
IPC分类号： G06F9/30
摘要： A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
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公开(公告)号：US10162639B2
公开(公告)日：2018-12-25
申请号：US15912498
申请日：2018-03-05
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
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公开(公告)号：US10162638B2
公开(公告)日：2018-12-25
申请号：US15912486
申请日：2018-03-05
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
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公开(公告)号：US10162637B2
公开(公告)日：2018-12-25
申请号：US15912468
申请日：2018-03-05
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
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公开(公告)号：US10095516B2
公开(公告)日：2018-10-09
申请号：US13538523
申请日：2012-06-29
申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
发明人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
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公开(公告)号：US09898283B2
公开(公告)日：2018-02-20
申请号：US13976580
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
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9.发明授权公开(公告)号：US09690591B2
公开(公告)日：2017-06-27
申请号：US12290395
申请日：2008-10-30
申请人： Ido Ouziel , Lihu Rappoport , Robert Valentine , Ron Gabor , Pankaj Raghuvanshi
发明人： Ido Ouziel , Lihu Rappoport , Robert Valentine , Ron Gabor , Pankaj Raghuvanshi
IPC分类号： G06F9/30 , G06F9/38 , G06F12/084 , G06F12/0875 , G06F13/40
CPC分类号： G06F9/3853 , G06F9/3016 , G06F9/3017 , G06F9/30196 , G06F9/3836 , G06F12/084 , G06F12/0875 , G06F13/4063 , G06F2212/452 , G06F2212/62 , Y02D10/14 , Y02D10/151
摘要： A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, processor logic delays the processing of a first instruction for a threshold amount of time if the first instruction within an instruction queue is fusible with a second instruction.
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公开(公告)号：US09678751B2
公开(公告)日：2017-06-13
申请号：US13977612
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Moustapha Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Boris Ginzburg , Ziv Aviv
发明人： Elmoustapha Ould-Ahmed-Vall , Moustapha Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Boris Ginzburg , Ziv Aviv
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30101
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal partial sum of packed data elements in response to a single vector packed horizontal sum instruction that includes a destination vector register operand, a source vector register operand, and an opcode are described.
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