公开(公告)号：US08452581B2

公开(公告)日：2013-05-28

申请号：US12436019

申请日：2009-05-05

Applicant: Krishnan Sundaresan ,  Pravin Chander Chandran

Inventor： Krishnan Sundaresan ,  Pravin Chander Chandran

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: A method for estimating power consumption of a design block of an integrated circuit includes obtaining power consumption data from designs of older-generation microprocessors, selecting a set of power consumption parameters, applying a curve-fitting technique on the obtained power consumption data for the selected set of power consumption parameters, creating a new power consumption model based on the curve-fitting technique and one or more of the power consumption parameters, using the model at a register transfer level of a newer-generation microprocessor to represent estimates of register transfer level power consumption of the newer-generation microprocessor, and outputting the register transfer level power consumption estimates based on the model.

Abstract translation: 一种用于估计集成电路的设计块的功耗的方法包括从旧式微处理器的设计中获得功耗数据，选择一组功耗参数，对所选择的所获得的功耗数据应用曲线拟合技术 一组功耗参数，基于曲线拟合技术和一个或多个功耗参数创建新的功耗模型，使用新一代微处理器的寄存器传输级别的模型来表示寄存器传输级别的估计 新一代微处理器的功耗，并基于该模型输出寄存器传输级功耗估计。

公开(公告)号：US20100286974A1

公开(公告)日：2010-11-11

申请号：US12436019

申请日：2009-05-05

Applicant: Krishnan Sundaresan ,  Pravin Chander Chandran

Inventor： Krishnan Sundaresan ,  Pravin Chander Chandran

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: A method for estimating power consumption of a design block of an integrated circuit includes obtaining power consumption data from designs of older-generation microprocessors, selecting a set of power consumption parameters, applying a curve-fitting technique on the obtained power consumption data for the selected set of power consumption parameters, creating a new power consumption model based on the curve-fitting technique and one or more of the power consumption parameters, using the model at a register transfer level of a newer-generation microprocessor to represent estimates of register transfer level power consumption of the newer-generation microprocessor, and outputting the register transfer level power consumption estimates based on the model.

Abstract translation: 一种用于估计集成电路的设计块的功耗的方法包括从旧式微处理器的设计中获得功耗数据，选择一组功耗参数，对所选择的所获得的功耗数据应用曲线拟合技术 一组功耗参数，基于曲线拟合技术和一个或多个功耗参数创建新的功耗模型，使用新一代微处理器的寄存器传输级别的模型来表示寄存器传输级别的估计 新一代微处理器的功耗，并基于该模型输出寄存器传输级功耗估计。

公开(公告)号：US08225245B2

公开(公告)日：2012-07-17

申请号：US12609370

申请日：2009-10-30

Applicant: Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

Inventor： Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

IPC: G06F9/45

CPC classification number: G06F17/505 ,  G06F2217/78

Abstract: A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.

Abstract translation: 在半导体设计中合并门控时钟域的方法和系统包括：对初始的时钟选通功能集合中的时钟门控功能的每个子集产生一组定量的函数，其通过存在量化子集中的每个时钟门控函数产生 一组不是子集的其他时钟门控功能的支持集的一部分的变量。 如果一组量化函数相等，则选择一个作为超时钟门控功能，并将其添加到一组超时钟门控功能。 该超级时钟门控功能集合根据标准进行排序，并选择最佳选项并将其添加到最终时钟门控功能组中。 剩余的超级时钟门控功能被修改，以防止由所选择的超级时钟门控功能选通的触发器被剩余的超时钟门控功能选通。

公开(公告)号：US07802217B1

公开(公告)日：2010-09-21

申请号：US12011310

申请日：2008-01-25

Applicant: Venkatesh P. Gopinath ,  Krishnan Sundaresan ,  Jaewon Oh ,  Ke Peng ,  Robert E. Mains

Inventor： Venkatesh P. Gopinath ,  Krishnan Sundaresan ,  Jaewon Oh ,  Ke Peng ,  Robert E. Mains

IPC: G06F9/45 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/78

Abstract: Broadly speaking, the embodiments of the present invention fill the need for a method of designing semiconductor device chips with reduced power consumption. The embodiments describe methods that are activity-based and are used for power optimization. The embodiments provide methods of selecting instances of a block of a chip to be replaced by either gate-length bias (GBIAS) cells or high-threshold-voltage (HVT) cells with minimal impact (little or no impact) on the overall performance of the chip. Only instances not on the critical path(s) are selected. Instances with low activities and high slack thresholds are chosen to be replaced by either GBIAS cells or HVT cells. By replacing the instances with low activities and high slack threshold, the performance impact on the block and chip is minimized. The replacement results in net power reduction, which is critical to advanced device technologies.

Abstract translation: 广义而言，本发明的实施例满足了对降低功耗设计半导体器件芯片的方法的需求。 实施例描述了基于活动并且用于功率优化的方法。 这些实施例提供了选择将由栅极长度偏置（GBIAS）单元或高阈值电压（HVT）单元替换的芯片块的实例的方法，该单元具有最小影响（很小或没有影响）对整体性能的影响 芯片。 仅选择不在关键路径上的实例。 选择具有低活性和高松弛阈值的实例被GBIAS细胞或HVT细胞替代。 通过替换具有低活动和高松弛阈值的实例，对块和芯片的性能影响最小化。 替代产生了净功率降低，这对先进的器件技术至关重要。

公开(公告)号：US08533648B2

公开(公告)日：2013-09-10

申请号：US12779891

申请日：2010-05-13

Applicant: Krishnan Sundaresan ,  Aravind Oommen

Inventor： Krishnan Sundaresan ,  Aravind Oommen

IPC: G06F17/50

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/3275 ,  Y02D10/128 ,  Y02D10/14

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a description of a circuit that includes clocked memory elements, some of which are clock-gated. Next, the system identifies a sender memory element by identifying a sender path from an output of the sender memory element to a data input for a seed memory element. Then, the system identifies an enable-generating memory element by identifying an enable-signal path from an output of the enable-generating memory element to an enable signal which is used to gate a clock signal input for the seed memory element. Next, the system provides clock-gating for the sender memory element by generating an enable signal using a data input for the enable-generating memory element. Finally, the system gates a clock signal for the sender memory element using this generated enable signal.

Abstract translation: 本发明的实施例提供了一种用于时钟门控电路的方法和系统。 在操作期间，系统接收包括时钟存储器元件的电路的描述，其中一些是时钟门控的。 接下来，系统通过识别从发送者存储器元件的输出到种子存储器元件的数据输入的发送器路径来识别发送者存储器元件。 然后，该系统通过从使能产生存储器元件的输出识别使能信号路径识别出使能信号路径，该使能信号路径被用于对输入种子存储器元件的时钟信号进行选通。 接下来，系统通过使用用于产生能量的存储器元件的数据输入产生使能信号来为发送器存储器元件提供时钟门控。 最后，系统使用该产生的使能信号来为发送器存储元件门控一个时钟信号。

公开(公告)号：US20110283125A1

公开(公告)日：2011-11-17

申请号：US12779891

申请日：2010-05-13

Applicant: Krishnan Sundaresan ,  Aravind Oommen

Inventor： Krishnan Sundaresan ,  Aravind Oommen

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/3275 ,  Y02D10/128 ,  Y02D10/14

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a description of a circuit that includes clocked memory elements, some of which are clock-gated. Next, the system identifies a sender memory element by identifying a sender path from an output of the sender memory element to a data input for a seed memory element. Then, the system identifies an enable-generating memory element by identifying an enable-signal path from an output of the enable-generating memory element to an enable signal which is used to gate a clock signal input for the seed memory element. Next, the system provides clock-gating for the sender memory element by generating an enable signal using a data input for the enable-generating memory element. Finally, the system gates a clock signal for the sender memory element using this generated enable signal.

Abstract translation: 本发明的实施例提供了一种用于时钟门控电路的方法和系统。 在操作期间，系统接收包括时钟存储器元件的电路的描述，其中一些是时钟门控的。 接下来，系统通过识别从发送者存储器元件的输出到种子存储器元件的数据输入的发送器路径来识别发送者存储器元件。 然后，该系统通过从使能产生存储器元件的输出识别使能信号路径识别出使能信号路径，该使能信号路径被用于对输入种子存储器元件的时钟信号进行选通。 接下来，系统通过使用用于产生能量的存储器元件的数据输入产生使能信号来为发送器存储器元件提供时钟门控。 最后，系统使用该产生的使能信号来为发送器存储元件门控一个时钟信号。

公开(公告)号：US08380656B2

公开(公告)日：2013-02-19

申请号：US12610194

申请日：2009-10-30

Applicant: Krishnan Sundaresan ,  Wei-Lun Hung ,  Jaewon Oh ,  Robert E. Mains

Inventor： Krishnan Sundaresan ,  Wei-Lun Hung ,  Jaewon Oh ,  Robert E. Mains

IPC: G06F15/00 ,  G06F15/18 ,  G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/78 ,  G06N7/005

Abstract: A method for computing power consumption includes querying a software database for a key node and a gate comprising an input port, connected to the key node, and an output port. The software database is created from a net list associated with a design. The method includes calculating a probability of activity level at the output port based on a predetermined activity level at the key node, and querying the software database for next gate comprising a next input port, connected to the previous output port, and a next output port. The method includes calculating a probability of activity level at the next output port based on the probability of activity level at the previous output port. The method includes computing a sub-circuit gate power by sum of power of all the gates based on the probability of activity level at output ports of the gates.

Abstract translation: 一种用于计算功耗的方法包括查询关键节点的软件数据库和包括连接到密钥节点的输入端口和输出端口的门。 软件数据库是从与设计相关联的网络列表创建的。 该方法包括基于关键节点处的预定活动级别计算输出端口处的活动级别的概率，并且向软件数据库查询包括连接到先前输出端口的下一个输入端口和下一个输出端口的下一个门 。 该方法包括基于先前输出端口的活动级别的概率来计算下一个输出端口处的活动级别的概率。 该方法包括基于门的输出端口处的活动级别的概率来计算所有门的功率之和的子电路门功率。

公开(公告)号：US08132144B2

公开(公告)日：2012-03-06

申请号：US12486171

申请日：2009-06-17

Applicant: Krishnan Sundaresan ,  Aravind Oommen

Inventor： Krishnan Sundaresan ,  Aravind Oommen

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/14

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a circuit which includes a plurality of clocked memory elements. Next, the system identifies a feedback path from an output of a clocked memory element to an input of the clocked memory element, wherein the feedback path passes through intervening combinational logic, but does not pass through other clocked memory elements in the circuit. Then, the system gates a clock signal to the clocked memory element so that the clock signal is disabled when the feedback path causes a value which appears at the output of the clocked memory element to be appear at the input of the clocked memory element.

Abstract translation: 本发明的实施例提供了一种用于时钟门控电路的方法和系统。 在操作期间，系统接收包括多个计时存储元件的电路。 接下来，系统识别从时钟存储元件的输出到时钟控制的存储器元件的输入的反馈路径，其中反馈路径通过中间组合逻辑，但不通过电路中的其它时钟存储元件。 然后，系统将时钟信号向定时存储元件施加门限，使得当反馈路径导致出现在时钟存储器元件的输出处的值出现在时钟控制的存储器元件的输入端时，时钟信号被禁止。

公开(公告)号：US20110106748A1

公开(公告)日：2011-05-05

申请号：US12610194

申请日：2009-10-30

Applicant: Krishnan Sundaresan ,  Wei-Lun Hung ,  Jaewon Oh ,  Robert E. Mains

Inventor： Krishnan Sundaresan ,  Wei-Lun Hung ,  Jaewon Oh ,  Robert E. Mains

IPC: G06N7/02

CPC classification number: G06F17/5036 ,  G06F2217/78 ,  G06N7/005

Abstract: A method for computing power consumption includes querying a software database for a key node and a gate comprising an input port, connected to the key node, and an output port. The software database is created from a net list associated with a design. The method includes calculating a probability of activity level at the output port based on a predetermined activity level at the key node, and querying the software database for next gate comprising a next input port, connected to the previous output port, and a next output port. The method includes calculating a probability of activity level at the next output port based on the probability of activity level at the previous output port. The method includes computing a sub-circuit gate power by sum of power of all the gates based on the probability of activity level at output ports of the gates.

Abstract translation: 一种用于计算功耗的方法包括查询关键节点的软件数据库和包括连接到密钥节点的输入端口和输出端口的门。 软件数据库是从与设计相关联的网络列表创建的。 该方法包括基于密钥节点处的预定活动级别来计算输出端口处的活动级别的概率，并且向软件数据库查询包括连接到先前输出端口的下一个输入端口和下一个输出端口的下一个门 。 该方法包括基于先前输出端口的活动级别的概率来计算下一个输出端口处的活动级别的概率。 该方法包括基于门的输出端口处的活动级别的概率来计算所有门的功率之和的子电路门功率。

公开(公告)号：US20100325452A1

公开(公告)日：2010-12-23

申请号：US12486171

申请日：2009-06-17

Applicant: Krishnan Sundaresan ,  Aravind Oommen

Inventor： Krishnan Sundaresan ,  Aravind Oommen

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/14

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a circuit which includes a plurality of clocked memory elements. Next, the system identifies a feedback path from an output of a clocked memory element to an input of the clocked memory element, wherein the feedback path passes through intervening combinational logic, but does not pass through other clocked memory elements in the circuit. Then, the system gates a clock signal to the clocked memory element so that the clock signal is disabled when the feedback path causes a value which appears at the output of the clocked memory element to be appear at the input of the clocked memory element.

Abstract translation: 本发明的实施例提供了一种用于时钟门控电路的方法和系统。 在操作期间，系统接收包括多个计时存储元件的电路。 接下来，系统识别从时钟存储元件的输出到时钟控制的存储器元件的输入的反馈路径，其中反馈路径通过中间组合逻辑，但不通过电路中的其它时钟存储元件。 然后，系统将时钟信号向定时存储元件施加门限，使得当反馈路径导致出现在时钟存储器元件的输出处的值出现在时钟控制的存储器元件的输入端时，时钟信号被禁止。