公开(公告)号：US6147919A

公开(公告)日：2000-11-14

申请号：US274245

申请日：1999-03-23

申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C7/12 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C7/12

摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.

摘要翻译： 半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器 涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。 读出放大器在每行中分组成读出放大器模块。 只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器 。 本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。 只写列选择线由用于控制读出放大器的信号控制。

公开(公告)号：US6141274A

公开(公告)日：2000-10-31

申请号：US340145

申请日：1999-06-28

申请人： Satoshi Eto ,  Masato Matsumiya ,  Yuichi Uzawa ,  Kuninori Kawabata ,  Akira Kikutake ,  Toru Koga

发明人： Satoshi Eto ,  Masato Matsumiya ,  Yuichi Uzawa ,  Kuninori Kawabata ,  Akira Kikutake ,  Toru Koga

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C7/1039 ,  G11C7/1051

摘要： In a semiconductor integrated circuit having the function of executing a pre-charge operation of a data bus when data is transferred to the data bus from a plurality of driver circuits connected to the data bus, a reset circuit for executing the pre-charge operation of the data bus is constituted so as to start the pre-charge operation of the data bus upon receiving an end timing of a strobe signal. Preferably, the reset circuit detects that the data bus reaches a pre-charge level for executing the pre-charge operation, and then terminates the pre-charge operation. On the other hand, in a semiconductor integrated circuit having a data latch function by a pipeline system when the data is read out from a memory cell, etc., in synchronism with a clock, a plurality of latch circuit units for temporarily storing the data are disposed in a data read path, and each of these latch circuit units is constituted in such a manner as to allow the data to pass, as such, when a control signal for controlling data latch is inputted, and to latch the data when the control signal is not inputted.

摘要翻译： 在具有从数据总线连接的多个驱动电路向数据总线传送数据时执行数据总线的预充电动作的半导体集成电路中，执行预充电动作的复位电路 数据总线被构成为在接收到选通信号的结束定时时开始数据总线的预充电操作。 优选地，复位电路检测到数据总线达到用于执行预充电操作的预充电水平，然后终止预充电操作。 另一方面，在与时钟同步地从存储单元读出数据时，在具有流水线系统的数据锁存功能的半导体集成电路中，用于临时存储数据的多个锁存电路单元 被布置在数据读取路径中，并且这些锁存电路单元中的每一个被构成为允许数据通过，当用于控制数据锁存器的控制信号被输入时，并且当数据被锁定时锁存数据 不输入控制信号。

公开(公告)号：US6130849A

公开(公告)日：2000-10-10

申请号：US300269

申请日：1999-04-27

申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Yuichi Uzawa ,  Toru Koga ,  Akira Kikutake

发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Yuichi Uzawa ,  Toru Koga ,  Akira Kikutake

IPC分类号： G11C11/413 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/02

CPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229

摘要： In a data bus amplifier activation method for a semiconductor memory device having a memory cell array, a column selection circuit for selecting a column in the memory cell array, a read data bus for transferring read data, output from the column selected by the column selection circuit, to a read data bus amplifier, and a write data bus for transferring write data, output from a write data bus amplifier, to the column selected by the column selection circuit, the read data bus amplifier or the write data bus amplifier is activated by detecting the selection of the column effected by the column selection circuit. By so doing, a read data bus amplifier enable signal or a write data bus amplifier enable signal can be generated after the occurrence of a column select signal, eliminating the need to allow a large margin for the generation timing of the read data bus amplifier enable signal or the write data bus amplifier enable signal, and as a result, the operating speed of the semiconductor memory device can be increased.

摘要翻译： 在具有存储单元阵列的半导体存储器件的数据总线放大器激活方法中，用于选择存储单元阵列中的列的列选择电路，用于传送读数据的读数据总线，由列选择 电路，读取数据总线放大器以及用于将从数据总线放大器输出的写数据传送到由列选择电路选择的列的写数据总线，读数据总线放大器或写数据总线放大器被激活 通过检测由列选择电路实现的列的选择。 通过这样做，读数据总线放大器使能信号或写数据总线放大器使能信号可以在出现列选择信号之后产生，消除了对读数据总线放大器使能的产生定时的大余量 信号或写数据总线放大器使能信号，结果可以提高半导体存储器件的工作速度。

公开(公告)号：US07281155B1

公开(公告)日：2007-10-09

申请号：US09359767

申请日：1999-07-22

申请人： Satoshi Eto ,  Masato Matsumiya ,  Toshimi Ikeda ,  Yuki Ishii ,  Akira Kikutake ,  Kuninori Kawabata

发明人： Satoshi Eto ,  Masato Matsumiya ,  Toshimi Ikeda ,  Yuki Ishii ,  Akira Kikutake ,  Kuninori Kawabata

IPC分类号： H02H3/05

CPC分类号： G11C29/78

摘要： A semiconductor memory device having a shift redundancy function includes a switch circuit for changeably connecting a plurality of decode signal lines decoding an address signal to a plurality of selecting lines and redundancy selecting lines, and executes a switch operation for shifting at least one of a plurality of decode lines in the direction of a first redundancy selecting line positioned at one of the ends among a plurality of selecting lines or a second switch operation for shifting at least one of the decode lines in the direction of a second redundancy selecting line positioned at the other end among the selecting lines or both of the first and second operations when any fault occurs in a plurality of selecting lines. The semiconductor memory device preferably includes two or more first redundancy selecting lines positioned at one of the ends of a plurality of selecting lines, two or more second redundancy selecting lines positioned at the other end, and first and second switch units disposed in two stages. When any fault selecting line occurs, the first switch unit executes a first switch operation for shifting at least one of the decode signal lines in the direction of the first redundancy selecting line or a second switch operation for shifting the same in the direction of the second redundancy selecting line, or the second switch unit executes a third switch operation for shifting at least one decode signal line in the direction of the first redundancy selecting line or a fourth switch operation for shifting it in the direction of the second redundancy selecting line.

摘要翻译： 具有移位冗余功能的半导体存储器件包括用于将解码地址信号的多条解码信号线与多条选择线和冗余选择线可变地连接的开关电路，并且执行用于移位多个选择线和冗余选择线中的至少一个的切换操作 在位于多个选择线中的一端的第一冗余选择线的方向上的解码线的第二切换操作或用于沿着位于所述多个选择线的第二冗余选择线的方向移位至少一条解码线的第二切换操作 在多个选择线中发生任何故障时，选择线中的另一端或第一和第二操作两者。 半导体存储器件优选地包括位于多个选择线的一端的两个或更多个第一冗余选择线，以及位于另一端的两个或更多个第二冗余选择线以及分两个阶段布置的第一和第二开关单元。 当发生任何故障选择线时，第一开关单元执行第一开关操作，用于沿第一冗余选择线的方向移位至少一个解码信号线，或者执行第二开关操作，以使其在第二冗余选择线的方向上移位 冗余选择线或者第二开关单元执行用于在第一冗余选择线的方向上移位至少一个解码信号线的第三开关操作或者用于在第二冗余选择线的方向上移位的第四开关操作。

公开(公告)号：US06212091B1

公开(公告)日：2001-04-03

申请号：US09514313

申请日：2000-02-28

申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Akira Kikutake

发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Akira Kikutake

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C7/10

摘要： A semiconductor memory device has data bus lines which are connected to a memory cell array, and column selection lines, each of which is used to select a column of the memory cell array. The semiconductor memory device includes a shielding line placed between the column selection line and a data bus line adjacent to the column selection line. The shielding line electrically shields the data bus line from the column selection line. Therefore, the semiconductor memory device having the high speed data bus can be achieved because the coupling capacitance between the column selection line and the data bus line is reduced.

摘要翻译： 半导体存储器件具有连接到存储器单元阵列的数据总线和用于选择存储单元阵列的列的列选择线。 半导体存储器件包括放置在列选择线和与列选择线相邻的数据总线之间的屏蔽线。 屏蔽线将数据总线线与列选择线电屏蔽。 因此，由于列选择线与数据总线之间的耦合电容减小，所以可以实现具有高速数据总线的半导体存储器件。

公开(公告)号：US06643805B1

公开(公告)日：2003-11-04

申请号：US09568123

申请日：2000-05-10

申请人： Akira Kikutake ,  Masato Matsumiya ,  Satoshi Eto ,  Kuninori Kawabata

发明人： Akira Kikutake ,  Masato Matsumiya ,  Satoshi Eto ,  Kuninori Kawabata

IPC分类号： G11C2900

CPC分类号： G11C29/40 ,  G11C2029/2602

摘要： The present invention is a memory circuit which selects N number of segments out of M number of segments (N

摘要翻译： 本发明是在正常读取期间从M个片段（N

公开(公告)号：US06226203B1

公开(公告)日：2001-05-01

申请号：US09502470

申请日：2000-02-11

申请人： Akira Kikutake ,  Masato Matsumiya ,  Satoshi Eto ,  Kuninori Kawabata

发明人： Akira Kikutake ,  Masato Matsumiya ,  Satoshi Eto ,  Kuninori Kawabata

IPC分类号： G11C700

CPC分类号： G11C7/10

摘要： It is one aspect of the present invention to split a common data bus established in common for a plurality of segments into a read-dedicated common data bus and a write dedicated common data bus, in a memory device comprising a plurality of segments each of which includes a plurality of memory cells. With such a constitution, write data can be supplied to the write data bus even when read data are present on the read common data bus due to a read operation; and even when operation frequencies increase, there are no limitations to the timing of write operations following reading and the speed of write operations following reading can be increased.

摘要翻译： 本发明的一个方面是将在多个段中共同建立的公用数据总线分成读专用公用数据总线和写专用公用数据总线，在包括多个段的存储器件中， 包括多个存储单元。 通过这样的结构，即使读取的公共数据总线上的读取数据由于读取操作，也可以将写入数据提供给写入数据总线; 并且即使在操作频率增加的情况下，读取之后的写入操作的定时也没有限制，并且读取之后的写入操作的速度可以增加。

公开(公告)号：US06188625B1

公开(公告)日：2001-02-13

申请号：US09461721

申请日：1999-12-16

申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Akira Kikutake

发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Akira Kikutake

IPC分类号： G11C1300

CPC分类号： G11C11/4091

摘要： For cutting off a path for flowing a read detection current from a high-potential power supply (Vii) of a read data bus amplifier (S/B 33) to the ground side of a read controller (41) via a sense amplifier (31) selected based on an address in a write to a memory cell, a semiconductor memory device have a logic circuit (42, 43) for calculating logic between a block select signal and a write status signal to change the potential at the read controller (41) to the same power supply potential as that at the S/B (33) when the write status signal is activated. This logic circuit can prevent any unwanted read detection current from flowing in a data write, so as to suppress current consumption in a write.

摘要翻译： 为了切断用于将读取检测电流从读取数据总线放大器（S / B 33）的高电位电源（Vii）经由读出放大器（31）读取到读取控制器（41）的接地侧的路径 ），半导体存储器件具有用于计算块选择信号和写入状态信号之间的逻辑的逻辑电路（42,43），以改变读取控制器（41）处的电位 ）与写入状态信号被激活时，与S / B（33）的电源电位相同。 该逻辑电路可以防止任何不需要的读取检测电流在数据写入中流动，从而抑制写入中的电流消耗。

公开(公告)号：US20090077432A1

公开(公告)日：2009-03-19

申请号：US12273270

申请日：2008-11-18

申请人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

发明人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

IPC分类号： G06F11/00 ,  G11C29/04 ,  G06F11/07

CPC分类号： G11C29/42 ,  G11C11/41

摘要： Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

摘要翻译： 公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。 半导体存储器件具有计数器，寄存器和比较电路。 计数器对错误更正次数进行计数。 当外部输入上限设定信号（在图1所示的情况下为外部上限获取信号）以改变误差修正次数的上限时，该寄存器改变上限值。 比较电路将误差校正次数与改变的上限进行比较。

公开(公告)号：US07467337B2

公开(公告)日：2008-12-16

申请号：US11102715

申请日：2005-04-11

申请人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

发明人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

IPC分类号： G06F11/00

CPC分类号： G11C29/42 ,  G11C11/41

摘要： Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

摘要翻译： 公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。 半导体存储器件具有计数器，寄存器和比较电路。 计数器对错误更正次数进行计数。 当外部输入上限设定信号以改变误差修正次数的上限时，寄存器改变上限值。 比较电路将误差校正次数与改变的上限进行比较。