公开(公告)号：US20090242907A1

公开(公告)日：2009-10-01

申请号：US12408875

申请日：2009-03-23

申请人： Kunio HOSOYA ,  Saishi FUJIKAWA ,  Takahiro KASAHARA

发明人： Kunio HOSOYA ,  Saishi FUJIKAWA ,  Takahiro KASAHARA

IPC分类号： H01L33/00 ,  H01L21/18

CPC分类号： H01L21/84 ,  G02F2202/105 ,  H01L27/3262 ,  H01L27/3293 ,  H01L29/66772 ,  H01L51/52

摘要： To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor substrates to form a plurality of regions each comprising a single crystal semiconductor film over the base substrate; forming a plurality of transistors each comprising the single crystal semiconductor film as a channel formation region; and forming a plurality of pixel electrodes over the region provided with the single crystal semiconductor film and a region not provided with the single crystal semiconductor film. Some of the transistors electrically connecting to the pixel electrodes formed over the region not provided with the single crystal semiconductor film are formed in the region provided with the single crystal semiconductor film.

摘要翻译： 为了实现显示部分的放大和高清晰度，在像素中使用单晶半导体膜作为晶体管，并且包括以下步骤：将多个单晶半导体衬底接合到基底衬底; 分离所述多个单晶半导体衬底的一部分以在所述基底衬底上形成各自包括单晶半导体膜的多个区域; 形成各自包含所述单晶半导体膜作为沟道形成区域的多个晶体管; 以及在设置有单晶半导体膜的区域和未设置单晶半导体膜的区域上形成多个像素电极。 电连接到形成在未设置单晶半导体膜的区域上的像素电极的一些晶体管形成在设置有单晶半导体膜的区域中。

公开(公告)号：US20120299027A1

公开(公告)日：2012-11-29

申请号：US13567215

申请日：2012-08-06

申请人： Kunio HOSOYA ,  Saishi FUJIKAWA ,  Takahiro KASAHARA

发明人： Kunio HOSOYA ,  Saishi FUJIKAWA ,  Takahiro KASAHARA

IPC分类号： H01L33/62

CPC分类号： H01L21/84 ,  G02F2202/105 ,  H01L27/3262 ,  H01L27/3293 ,  H01L29/66772 ,  H01L51/52

摘要： To achieve enlargement and high definition of a display portion, a single crystal semiconductor film is used as a transistor in a pixel, and the following steps are included: bonding a plurality of single crystal semiconductor substrates to a base substrate; separating part of the plurality of single crystal semiconductor substrates to form a plurality of regions each comprising a single crystal semiconductor film over the base substrate; forming a plurality of transistors each comprising the single crystal semiconductor film as a channel formation region; and forming a plurality of pixel electrodes over the region provided with the single crystal semiconductor film and a region not provided with the single crystal semiconductor film. Some of the transistors electrically connecting to the pixel electrodes formed over the region not provided with the single crystal semiconductor film are formed in the region provided with the single crystal semiconductor film.

摘要翻译： 为了实现显示部分的放大和高清晰度，在像素中使用单晶半导体膜作为晶体管，并且包括以下步骤：将多个单晶半导体衬底接合到基底衬底; 分离所述多个单晶半导体衬底的一部分以在所述基底衬底上形成各自包括单晶半导体膜的多个区域; 形成各自包含所述单晶半导体膜作为沟道形成区域的多个晶体管; 以及在设置有单晶半导体膜的区域和未设置单晶半导体膜的区域上形成多个像素电极。 电连接到形成在未设置单晶半导体膜的区域上的像素电极的一些晶体管形成在设置有单晶半导体膜的区域中。

公开(公告)号：US20110260159A1

公开(公告)日：2011-10-27

申请号：US13173559

申请日：2011-06-30

申请人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

发明人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC分类号： H01L29/12

CPC分类号： H01L29/7869 ,  H01L27/0266 ,  H01L27/1225 ,  H01L27/124

摘要： The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.

摘要翻译： 保护电路使用非线性元件形成，该非线性元件包括覆盖栅电极的栅极绝缘膜; 第一布线层和第二布线层，其在栅极绝缘膜上方并且其端部与栅电极重叠; 以及氧化物半导体层，其在所述栅电极的上方并与所述栅极绝缘膜和所述第一布线层和所述第二布线层的端部接触。 非线性元件的栅电极和扫描线或信号线包括在布线中，非线性元件的第一或第二布线层直接连接到布线，以施加栅极的电位 电极。

公开(公告)号：US20100084653A1

公开(公告)日：2010-04-08

申请号：US12571552

申请日：2009-10-01

申请人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

发明人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L29/7869 ,  H01L27/0266 ,  H01L27/1225 ,  H01L27/124

摘要： The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.

摘要翻译： 保护电路使用非线性元件形成，该非线性元件包括覆盖栅电极的栅极绝缘膜; 第一布线层和第二布线层，其在栅极绝缘膜上方并且其端部与栅电极重叠; 以及氧化物半导体层，其在所述栅电极的上方并与所述栅极绝缘膜和所述第一布线层和所述第二布线层的端部接触。 非线性元件的栅电极和扫描线或信号线包括在布线中，非线性元件的第一或第二布线层直接连接到布线，以施加栅极的电位 电极。

公开(公告)号：US20100065840A1

公开(公告)日：2010-03-18

申请号：US12553168

申请日：2009-09-03

申请人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

发明人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC分类号： H01L33/00

CPC分类号： H01L27/0266 ,  G02F1/133305 ,  G02F1/1339 ,  G02F1/13394 ,  G02F1/134309 ,  G02F1/13624 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

摘要： A protective circuit includes a non-linear element, which further includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a conductive layer and a second oxide semiconductor layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with side face portions of the gate insulating layer and the conductive layer of the first wiring layer and the second wiring layer and a side face portion and a top face portion of the second oxide semiconductor layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.

摘要翻译： 保护电路包括非线性元件，其还包括栅电极，覆盖栅电极的栅极绝缘层，一对第一和第二布线层，其端部与栅极绝缘层上的栅极重叠，并且其中 堆叠导电层和第二氧化物半导体层，以及与至少栅电极重叠并与栅极绝缘层和第一布线层的导电层的侧面部分接触的第一氧化物半导体层和 第二布线层和第二氧化物半导体层的侧面部分和顶面部分。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

公开(公告)号：US20090140253A1

公开(公告)日：2009-06-04

申请号：US12325512

申请日：2008-12-01

申请人： Takahiro KASAHARA

发明人： Takahiro KASAHARA

IPC分类号： H01L29/04

CPC分类号： G02F1/134336 ,  G02F1/134309 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/52 ,  G09G3/3607 ,  G09G3/3611 ,  G09G3/3614 ,  G09G3/3659 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1266 ,  H01L27/3213 ,  H01L27/3218 ,  H01L27/326 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78654 ,  H01L51/5284

摘要： A new TFT arrangement is demonstrated, which enables prevention of TFT to be formed over a joint portion between the adjacent SOI layers prepared by the process including the separation of a thin single crystal semiconductor layer from a semiconductor wafer. The TFT arrangement is characterized by the structure where a plurality of TFTs each belonging to different pixels is gathered and arranged close to an intersection portion of a scanning line and a signal line. This structure allows the distance between regions, which are provided with the plurality of TFTs, to be extremely large compared with the distance between adjacent TFTs in the conventional TFT arrangement in which all TFTs are arranged in at a regular interval. The formation of a TFT over the joint portion can be avoided by the present arrangement, which leads to the formation of a display device with a negligible amount of display defects.

摘要翻译： 证明了一种新的TFT装置，其能够防止在通过包括从半导体晶片分离薄单晶半导体层的工艺制备的相邻SOI层之间的接合部分上形成TFT。 TFT装置的特征在于其中属于不同像素的多个TFT聚集并布置在扫描线和信号线的交叉部分附近的结构。 这种结构允许设置有多个TFT的区域之间的距离与其中所有TFT以规则间隔布置的常规TFT布置中的相邻TFT之间的距离相比非常大。 通过这种布置可以避免在接合部分上形成TFT，这导致形成具有可忽略的显示缺陷量的显示装置。

公开(公告)号：US20100084654A1

公开(公告)日：2010-04-08

申请号：US12571554

申请日：2009-10-01

申请人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

发明人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： G02F1/136204 ,  H01L27/0248 ,  H01L27/1225 ,  H01L27/124 ,  H01L33/0041 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode.

摘要翻译： 为了利用包括氧化物半导体的显示装置的特性，需要具有适当结构和占用面积小的保护电路等。 保护电路使用非线性元件形成，该非线性元件包括覆盖栅电极的栅极绝缘膜; 栅绝缘膜上的第一氧化物半导体层; 覆盖与第一氧化物半导体层的沟道形成区重叠的区域的沟道保护层; 以及通过层叠导电层和第二氧化物半导体层并在第一氧化物半导体层上形成的第一布线层和第二布线层。 栅电极连接到扫描线或信号线，第一布线层或第二布线层直接连接到栅电极。

公开(公告)号：US20100065839A1

公开(公告)日：2010-03-18

申请号：US12553122

申请日：2009-09-03

申请人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

发明人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC分类号： H01L33/00

CPC分类号： H01L27/1214 ,  G02F1/13624 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/78693

摘要： A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.

摘要翻译： 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，一对第一和第二布线层，其端部与栅极绝缘层上的栅电极重叠，并且其中 层叠第二氧化物半导体层和导电层，以及与至少栅电极重叠并与栅极绝缘层接触的第一氧化物半导体层，导电层的侧面部和顶面部的一部分，以及 在第一布线层和第二布线层中的第二氧化物半导体层的侧面部分。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

公开(公告)号：US20120300150A1

公开(公告)日：2012-11-29

申请号：US13567292

申请日：2012-08-06

申请人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

发明人： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC分类号： G02F1/1368 ,  H01L27/15

摘要： A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

摘要翻译： 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，与栅极绝缘层上的栅电极重叠的第一氧化物半导体层，以及第一布线层和第二布线层 其端部与第一氧化物半导体层上的栅电极重叠，并且其中层叠有导电层和第二氧化物半导体层。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

公开(公告)号：US20120012853A1

公开(公告)日：2012-01-19

申请号：US13244380

申请日：2011-09-24

申请人： Takahiro KASAHARA

发明人： Takahiro KASAHARA

IPC分类号： H01L29/786

CPC分类号： G02F1/134336 ,  G02F1/134309 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/52 ,  G09G3/3607 ,  G09G3/3611 ,  G09G3/3614 ,  G09G3/3659 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1266 ,  H01L27/3213 ,  H01L27/3218 ,  H01L27/326 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78654 ,  H01L51/5284

摘要： A new TFT arrangement is demonstrated, which enables prevention of TFT to be formed over a joint portion between the adjacent SOI layers prepared by the process including the separation of a thin single crystal semiconductor layer from a semiconductor wafer. The TFT arrangement is characterized by the structure where a plurality of TFTs each belonging to different pixels is gathered and arranged close to an intersection portion of a scanning line and a signal line. This structure allows the distance between regions, which are provided with the plurality of TFTs, to be extremely large compared with the distance between adjacent TFTs in the conventional TFT arrangement in which all TFTs are arranged in at a regular interval. The formation of a TFT over the joint portion can be avoided by the present arrangement, which leads to the formation of a display device with a negligible amount of display defects.

摘要翻译： 证明了一种新的TFT装置，其能够防止在通过包括从半导体晶片分离薄单晶半导体层的工艺制备的相邻SOI层之间的接合部分上形成TFT。 TFT装置的特征在于其中属于不同像素的多个TFT聚集并布置在扫描线和信号线的交叉部分附近的结构。 这种结构允许设置有多个TFT的区域之间的距离与其中所有TFT以规则间隔布置的常规TFT布置中的相邻TFT之间的距离相比非常大。 通过这种布置可以避免在接合部分上形成TFT，这导致形成具有可忽略的显示缺陷量的显示装置。