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公开(公告)号：US06384446B2
公开(公告)日：2002-05-07
申请号：US09024601
申请日：1998-02-17
IPC分类号： H01L2976
CPC分类号： H01L28/90 , H01L27/10855
摘要： An improved method of capacitor formation is disclosed. A dielectric is etched with an etch recipe which creates grooves within an opening. The opening is filled with metal which conforms to the grooves, thereby creating a capacitor's lower plate with increased surface area. The metal is later surrounded with dielectric and metal, which forms respectively the capacitor's dielectric and upper plate.
摘要翻译： 公开了改进的电容器形成方法。 用蚀刻配方蚀刻电介质，其在开口内产生凹槽。 开口填充符合槽的金属，从而形成具有增加的表面积的电容器的下板。 金属后来被电介质和金属包围，分别形成电容器的电介质和上板。
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公开(公告)号：US5849639A
公开(公告)日：1998-12-15
申请号：US979297
申请日：1997-11-26
IPC分类号： H01L21/302 , B08B7/00 , G03F7/42 , H01L21/304 , H01L21/311 , H01L21/3065
CPC分类号： H01L21/02063 , B08B7/0035 , G03F7/427 , H01L21/31138 , Y10S438/906
摘要： A gas plasma process for removing photoresist and etch residues and other contaminants involved in etching vias in integrated circuit devices is disclosed. The process involves placing the substrate having etched vias or contact holes in a suitable low bias reactor; applying to the substrate surface a mixture of gases at low bias selected from the group consisting of oxygen, nitrogen, fluorine, hydrofluorocarbon and fluorinated methane and amine gases to both remove the photoresist layer and alter the composition of the residues such that the residues are soluble in water; and rinsing the substrate with deionized water. The plasma process should be carried out at temperatures of less than about 100 degrees C to avoid mobile ion contamination problems and oxidation of the etch residues.
摘要翻译： 公开了一种用于去除光刻胶和蚀刻残留物和涉及在集成电路器件中的通孔中的其它污染物的气体等离子体工艺。 该方法包括将具有蚀刻过孔或接触孔的基板放置在合适的低偏压反应器中; 以低偏压选择氧气，氮气，氟气，氢氟碳氟化合物和氟化甲烷和胺气体，向基板表面施加气体混合物，以去除光致抗蚀剂层并改变残留物的组成，使残留物溶解 在水里; 并用去离子水冲洗底物。 等离子体处理应在低于约100摄氏度的温度下进行，以避免移动离子污染问题和蚀刻残留物的氧化。
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公开(公告)号：US6046115A
公开(公告)日：2000-04-04
申请号：US164283
申请日：1998-10-01
IPC分类号： H01L21/302 , B08B7/00 , G03F7/42 , H01L21/304 , H01L21/311 , H01L21/3065
CPC分类号： H01L21/02063 , B08B7/0035 , G03F7/427 , H01L21/31138 , Y10S438/906
摘要： A gas plasma process without argon sputtering for removing photoresist, etch residues and other contaminants involved in etching vias in integrated circuit devices is disclosed. The process involves placing the substrate having etched vias or contact holes in a suitable low bias reactor; applying to the substrate surface a mixture of gases at low bias selected from the group consisting of oxygen, nitrogen, fluorine, hydrofluorocarbon and fluorinated methane and amine gases to both remove the photoresist layer and alter the composition of the residues such that the residues are soluble in water; and rinsing the substrate with deionized water. The plasma process should be carried out at temperatures of less than about 100 degrees C. to avoid mobile ion contamination problems and oxidation of the etch residues.
摘要翻译： 公开了一种没有氩气溅射的气体等离子体工艺，用于去除在集成电路器件中蚀刻过孔中的光致抗蚀剂，蚀刻残余物和其它污染物 该方法包括将具有蚀刻过孔或接触孔的基板放置在合适的低偏压反应器中; 以低偏压选择氧气，氮气，氟气，氢氟碳氟化合物和氟化甲烷和胺气体，向基板表面施加气体混合物，以去除光致抗蚀剂层并改变残留物的组成，使残留物溶解 在水里; 并用去离子水冲洗底物。 等离子体处理应在小于约100摄氏度的温度下进行，以避免移动离子污染问题和蚀刻残留物的氧化。
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4.发明授权公开(公告)号：US06329281B1
公开(公告)日：2001-12-11
申请号：US09454909
申请日：1999-12-03
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/76813
摘要： The present invention utilizes a selective overlayer to provide more efficient fabrication of a dual damascene multilevel interconnect structure. The selective overlayer serves as a protective mask which prevents the upper layer of the composite layer from being eroded during the formation of the multi-level interconnects. The present invention also solves some of the problems associated with the full-via first and partial-via first fabrication methods because the selective overlayer enables an efficient, deep partial via to be formed while preventing the deposit of undeveloped photoresist in subsequent fabrication steps. The present invention also provides advantages during the planarization and polishing of the dual damascene structure after the deposition of the conductive layer because the selective overlayer allows for efficient planarization without loss of trench depth control.
摘要翻译： 本发明利用选择性覆盖层来提供更有效地制造双镶嵌多层互连结构。 选择性覆盖层用作保护掩模，其防止复合层的上层在形成多层互连期间被侵蚀。 本发明还解决了与全通孔第一和部分通孔第一制造方法相关的一些问题，因为选择性覆盖层能够形成有效的深部分通孔，同时防止在随后的制造步骤中沉积未显影的光致抗蚀剂。 本发明还在沉积导电层之后在双镶嵌结构的平面化和抛光期间提供了优点，因为选择性覆盖层允许有效的平面化而不损失沟槽深度控制。
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5.发明授权Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies 有权通过开尔文电阻测试结构堆叠，用于测量多级金属集成电路技术中的接触异常公开(公告)号：US06362638B1
公开(公告)日：2002-03-26
申请号：US09388203
申请日：1999-09-01
IPC分类号： G01R3126
CPC分类号： G01R31/04
摘要： A method and apparatus for measuring Kelvin contact resistance within an integrated circuit interconnect is provided, having upper and lower Kelvin contact resistance contacts covering a via and interconnect being measured, along with a third conductor placed substantially between the upper and lower Kelvin contacts, and in contact with the via.
摘要翻译： 提供了一种用于测量集成电路互连中的开尔文接触电阻的方法和装置，具有覆盖通过测量的通孔和互连的上开和下开口接触电阻触点，以及基本上位于上开和下开口触点之间的第三导体，以及 与通道接触。
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公开(公告)号：US06750495B1
公开(公告)日：2004-06-15
申请号：US09310388
申请日：1999-05-12
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L27/10852 , H01L28/55 , H01L28/91
摘要： A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor. The lower plate is then etched so that it is removed from a portion of the sidewalls and from the top surface of the dielectric layer. After the lower electrode is etched, a dielectric material is disposed in the cavity and on the top surface of the dielectric layer. A second layer of conductor is disposed on top of the dielectric material layer, thus completing the capacitor structure.
摘要翻译： 在集成电路的电介质层的窗口中形成电容器结构。 下电极（或板）设置在空腔的部分侧表面上，但不设置在电介质的顶表面上。 介电材料层设置在下电极上和集成电路电介质的顶表面上。 最后，在电介质材料层上设置上电极（或板）。 因为下部电极从空腔侧壁的一部分移除，并且避免了在平坦化期间可能导致的电介质短路问题的顶表面。 还公开了一种用于制造用于多层结构的集成电路（IC）的技术。 该技术很容易并入标准的多级处理技术。 在IC的特定电介质层中打开窗口之后，在窗口中沉积导电层并形成电容器的下板。 然后蚀刻下板，使其从侧壁的一部分和从电介质层的顶表面去除。 在蚀刻下部电极之后，介电材料设置在空腔中并在电介质层的顶表面上。 第二层导体设置在介电材料层的顶部，从而完成电容器结构。
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