公开(公告)号：US07412589B2

公开(公告)日：2008-08-12

申请号：US11278275

申请日：2006-03-31

申请人： Kurt Alan Feiste

发明人： Kurt Alan Feiste

IPC分类号： G06F7/38

CPC分类号： G06F9/3867 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline. Instruction flushes are counted in the pipeline to determine a flush count. A single step mode in the pipeline is entered in response to the flush count exceeding a threshold. The single step mode instructions are issued in serial such that an instruction is not issued for execution until a prior instruction has completed execution.

摘要翻译： 一种计算机实现的方法，装置和计算机可用程序代码，用于确保处理器流水线中的指令的前进进程。 正在接收指令。 在流水线中计数指令刷新以确定冲洗计数。 响应于冲洗计数超过阈值，输入流水线中的单步模式。 单步模式指令是以串行方式发出的，这样在一个先前的指令完成执行之前，不会执行指令执行。

公开(公告)号：US5822765A

公开(公告)日：1998-10-13

申请号：US572824

申请日：1995-12-14

申请人： Bryan David Boatright ,  Kurt Alan Feiste ,  Lawrence Joseph Merkel ,  Derek Edward Williams

发明人： Bryan David Boatright ,  Kurt Alan Feiste ,  Lawrence Joseph Merkel ,  Derek Edward Williams

IPC分类号： G06F12/08 ,  G06F13/376

CPC分类号： G06F12/0831

摘要： A data processing system and method having a number of cache controllers coupled to a bus. A cache controller uses a buffer operably coupled to the bus for loading information from the bus. A status bit associated with a buffer indicates the buffer status. The cache controller has logic circuitry operably coupled to the bus and the buffer. The logic circuitry responds to a certain cache coherency operation by loading the buffer and waiting during a predetermined interval for a possible retry signal before further processing the operation.

摘要翻译： 一种具有耦合到总线的多个高速缓存控制器的数据处理系统和方法。 高速缓存控制器使用可操作地耦合到总线的缓冲器来从总线加载信息。 与缓冲区相关联的状态位指示缓冲区状态。 高速缓存控制器具有可操作地耦合到总线和缓冲器的逻辑电路。 逻辑电路通过加载缓冲器并且在进一步处理该操作之前在预定间隔期间等待可能的重试信号来响应某个高速缓存一致性操作。

公开(公告)号：US08082423B2

公开(公告)日：2011-12-20

申请号：US11201683

申请日：2005-08-11

申请人： Christopher Michael Abernathy ,  Kurt Alan Feiste ,  David Scott Ray ,  David Shippy ,  Albert James Van Norstrand, Jr.

发明人： Christopher Michael Abernathy ,  Kurt Alan Feiste ,  David Scott Ray ,  David Shippy ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3885

摘要： A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions.

摘要翻译： 提供了一种用于检测和处理微处理器系统中的指令齐平的方法和装置。 提供了一种分布在数据处理系统中的所有执行单元的刷新机制。 冲洗机构不需要中央收集点将刷新信号重新分配给执行单元。 每个单元生成一个刷新向量到所有其他执行单元，用于阻止刷新指令的寄存器更新。

公开(公告)号：US07350056B2

公开(公告)日：2008-03-25

申请号：US11236838

申请日：2005-09-27

申请人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Kurt Alan Feiste ,  David Shippy

发明人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Kurt Alan Feiste ,  David Shippy

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3855

摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.

摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括以行和列配置的存储单元矩阵，包括耦合到执行单元的第一行。 显示从空行到无存储单元格时，逐行发行的说明。 当指示向第一行发出时，出现未占用的单元格。 当特定行包含一个尚未准备就绪的指令时，该指令发生停顿状态。 然而，为了防止整个问题队列和处理器停止，另一行中的就绪指令可能绕过包括已停止或尚未就绪的指令的行。 因此，对执行单元的指令的无序发布继续进行。

公开(公告)号：US5832276A

公开(公告)日：1998-11-03

申请号：US726947

申请日：1996-10-07

申请人： Kurt Alan Feiste ,  Thomas J. Somyak

发明人： Kurt Alan Feiste ,  Thomas J. Somyak

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0811

摘要： A L2 cache for resolving collisions between processor request originating from a processor and system request originating from a computing unit attached to the system bus is provided. First, the L2 cache snoops a system request to access a shared resource. This shared resource is often an area of main memory contained in the L2 cache. Next, the L2 cache receives a processor request to access the shared resource also. The L2 cache will delay sending an acknowledge signal to the processor. The L2 cache then makes a determination as to whether the address and system request type must be sent to the processor. If data associated with the system request would alter a line in a L1 cache associated with the processor, a retry signal is sent to the processor. If the system request would not alter a line in the L1 cache, the L2 cache will wait until the system request finishes accessing the shared resource to process the processor request, thereby avoiding the sending of a retry signal to the processor.

摘要翻译： 提供用于解决来自处理器的处理器请求与源自连接到系统总线的计算单元的系统请求之间的冲突的L2缓存。 首先，L2缓存侦听一个访问共享资源的系统请求。 该共享资源通常是包含在L2缓存中的主存储区域。 接下来，L2缓存也接收处理器请求以访问共享资源。 L2缓存将延迟向处理器发送确认信号。 然后，L2高速缓存确定地址和系统请求类型是否必须发送到处理器。 如果与系统请求相关联的数据将改变与处理器相关联的L1高速缓存中的行，则重试信号被发送到处理器。 如果系统请求不会改变L1缓存中的一行，则L2缓存将等待直到系统请求完成访问共享资源以处理处理器请求，从而避免向处理器发送重试信号。

公开(公告)号：US20080294885A1

公开(公告)日：2008-11-27

申请号：US12187279

申请日：2008-08-06

申请人： Kurt Alan Feiste

发明人： Kurt Alan Feiste

IPC分类号： G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline. Instruction flushes are counted in the pipeline to determine a flush count. A single step mode in the pipeline is entered in response to the flush count exceeding a threshold. The single step mode instructions are issued in serial such that an instruction is not issued for execution until a prior instruction has completed execution.

摘要翻译： 一种计算机实现的方法，装置和计算机可用程序代码，用于确保处理器流水线中的指令的前进进程。 正在接收指令。 在流水线中计数指令刷新以确定冲洗计数。 响应于冲洗计数超过阈值，输入流水线中的单步模式。 单步模式指令是以串行方式发出的，这样在一个先前的指令完成执行之前就不会执行指令执行。

公开(公告)号：US20080148021A1

公开(公告)日：2008-06-19

申请号：US12036704

申请日：2008-02-25

申请人： Jonathan James DeMent ,  Kurt Alan Feiste ,  Robert Alan Philhower ,  David Shippy

发明人： Jonathan James DeMent ,  Kurt Alan Feiste ,  Robert Alan Philhower ,  David Shippy

IPC分类号： G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3875

摘要： An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.

摘要翻译： 发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。 在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令 基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。 在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

公开(公告)号：US06349382B1

公开(公告)日：2002-02-19

申请号：US09263665

申请日：1999-03-05

申请人： Kurt Alan Feiste ,  Bruce Joseph Ronchetti ,  David James Shippy

发明人： Kurt Alan Feiste ,  Bruce Joseph Ronchetti ,  David James Shippy

IPC分类号： G06F1500

CPC分类号： G06F9/3834 ,  G06F9/3824

摘要： In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. When a load instruction is issued for execution, a determination is made whether the load instruction is attempting to load data to a memory location that is the same as a previously executed store instruction is waiting to complete. If so, then the data waiting to be stored within the cache by the store instruction is directly forwarded to the load instruction.

摘要翻译： 在微处理器内的加载/存储单元中，加载和存储指令是无序执行的。 加载和存储指令以预定方式分配标签，然后分配给加载和存储重新排序队列，以跟踪加载和存储指令的程序顺序。 当执行加载指令时，确定加载指令是否试图将数据加载到与先前执行的存储指令正在等待完成的存储单元相同的存储单元。 如果是这样，则通过存储指令等待存储在高速缓存内的数据被直接转发到加载指令。

公开(公告)号：US5926830A

公开(公告)日：1999-07-20

申请号：US726948

申请日：1996-10-07

申请人： Kurt Alan Feiste

发明人： Kurt Alan Feiste

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0811 ,  Y02B60/1225

摘要： A data processing system and method for maintaining coherency between a high-level (L2) cache and a low-level (L1) cache are disclosed. The L2 (high-level) cache operates in a first mode of operation where a cache line is in a modified and inclusive state, and in a second mode of operation where a cache line is in an invalid and inclusive state. The high-level cache snoops a request from another computing unit for access to data previously stored in the high-level cache. The high-level cache determines if the requested data stored in the high-level cache is invalid or modified, and possibly stored in the low-level cache. If the data is contained in the low-level cache and is modified, the data is returned from the low-level cache to the high-level cache, and from there is written to memory. In the first mode of operation, if no data is returned, and the data in the high-level cache is marked as modified, the data in the high-level cache is written to memory. In the second mode of operation, if no data is returned, the high-level cache does not write any data to memory. In another embodiment, the high-level cache utilizes the state of a line's low-level Inclusive bit when the cache line's MESI (modified, exclusive, shared, invalid) bits are set to the Invalid state. Data in the high-level cache is marked as possibly available in the low-level cache and invalid in the high-level cache. This allows for coherency to be maintained between the high-level and low-level caches without transferring data from the low-level cache to the high-level cache. The high level cache may also resolve collisions between a processor request and a system request originating from another computing unit and avoid sending a RETRY signal to the processor. An efficient pipelined algorithm for flushing the high level (L2) cache and back invalidating the low-level (L1) cache is described.

公开(公告)号：US5860100A

公开(公告)日：1999-01-12

申请号：US726949

申请日：1996-10-07

申请人： Kurt Alan Feiste ,  Thomas J. Somyak

发明人： Kurt Alan Feiste ,  Thomas J. Somyak

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0811

摘要： A L2 (high-level) cache according to the present invention implements an efficient pipelined algorithm for flushing the high-level cache and back-invalidating a L1 (low-level) cache. Initially, an address calculation stage calculates the address of a directory entry contained in an array of directory entries every clock cycle. Connected to this address calculation stage is a directory entry lookup stage. The directory entry lookup stage receives an address from the address calculation stage and retrieves the directory entry to be modified from the array of directory entries. Finally, a directory entry modification stage, connected to the directory entry lookup stage, receives the directory entry from the directory entry lookup stage. The directory entry modification stage first looks to see if the directory entry is not marked as invalid. If the directory entry is already marked as invalid, no further processing need be performed on the directory entry. If the directory entry modification stage determines the directory entry to not be invalid, the directory entry modification stage invalidates the directory entry to create a invalid directory entry. Next, the directory entry modification stage stores the invalid directory entry in the array of directory entries. The address calculation stage, the directory entry lookup stage, and the directory entry modification stage within the high-level cache can each perform a new operation every clock cycle. Also connected to the directory entry lookup stage is a castout stage. The castout stage receives a directory entry from the directory entry lookup stage and sends a flush signal to the processor. The flush signal directs the processor to invalidate a line in the low-level cache which corresponds to the directory entry. Also, the castout stage writes the modified contents of the high-level cache to memory.

摘要翻译： 根据本发明的L2（高级）高速缓存实现了用于刷新高级缓存并使L1（低级）高速缓存反向失效的有效流水线算法。 最初，地址计算阶段每个时钟周期计算目录条目数组中包含的目录条目的地址。 连接到该地址计算阶段是目录条目查找阶段。 目录条目查找阶段从地址计算阶段接收地址，并从目录条目数组中检索要修改的目录条目。 最后，连接到目录条目查找阶段的目录条目修改阶段从目录条目查找阶段接收目录条目。 目录条目修改阶段首先查看目录条目是否没有标记为无效。 如果目录条目已被标记为无效，则不需要在目录条目上执行进一步的处理。 如果目录条目修改阶段确定目录条目不为无效，则目录条目修改阶段会使目录条目无效以创建无效的目录条目。 接下来，目录条目修改阶段将无效目录条目存储在目录条目数组中。 高级缓存中的地址计算阶段，目录条目查找阶段和目录条目修改阶段可以每个时钟周期执行新的操作。 还连接到目录条目查找阶段是一个castout阶段。 castout阶段从目录条目查找阶段接收目录条目，并向处理器发送刷新信号。 刷新信号使处理器使低级缓存中对应于目录条目的行无效。 此外，退出阶段将高级缓存的修改内容写入内存。