Method for producing a semiconductor device having semiconductor layers
of SiC by the use of an ion-implantation technique
    1.
    发明授权
    Method for producing a semiconductor device having semiconductor layers of SiC by the use of an ion-implantation technique 失效
    通过使用离子注入技术制造具有SiC半导体层的半导体器件的方法

    公开(公告)号:US5705406A

    公开(公告)日:1998-01-06

    申请号:US636969

    申请日:1996-04-24

    摘要: A method for producing a semiconductor device having semiconductor layers of SiC with at least three doped layers on top of each other, comprises the steps of growing a first semiconductor layer of SiC; implanting an impurity dopant into the first layer to form a second doped surface layer as a sub-layer therein, the second doped surface layer being surrounded, except for the top surface thereof, by the first semiconductor layer; and epitaxially growing a third semiconductor layer of SiC on top of the second layer of SiC and regions of the first layer adjacent thereto to totally bury the second semiconductor layer. The impurity dopant implanted into the first semiconductor layer is of a first conductivity n or p type, and the first semiconductor layer being doped with a second, opposite conductivity type, so as to form a pn-junction at the interface between the first and second layers.

    摘要翻译: 一种用于制造半导体器件的方法,所述半导体器件具有在其顶部具有至少三个掺杂层的具有SiC的半导体层的半导体器件,包括生长SiC的第一半导体层的步骤; 将杂质掺杂剂注入到第一层中以形成第二掺杂表面层作为其中的子层,第二掺杂表面层除了其顶表面之外被第一半导体层包围; 在SiC的第二层的顶部和与其相邻的第一层的区域外部生长SiC的第三半导体层,以完全埋入第二半导体层。 注入到第一半导体层中的杂质掺杂物具有第一导电性n或p型,并且第一半导体层掺杂有第二相反导电型,从而在第一和第二导电类型之间的界面处形成pn结 层。

    PN-diode of SiC and a method for production thereof
    3.
    发明授权
    PN-diode of SiC and a method for production thereof 失效
    SiC的二极管及其制造方法

    公开(公告)号:US5902117A

    公开(公告)日:1999-05-11

    申请号:US859844

    申请日:1997-05-21

    摘要: A pn-diode of SiC has a first emitter layer part doped with first dopants having a low ionization energy and a second part designed as a grid and having portions extending vertically from above and past the junction between the drift layer and the first part and being laterally separated from each other by drift layer regions for forming a pn-junction by the first part and the drift layer adjacent such portions at a vertical distance from a lower end of the grid portions. The different parameters of the device are selected to allow a depletion of the drift layer in the blocking state form a continuous depleted region between the grid portions, to thereby screen off the high electric field at the pn-junction so that it will not be exposed to high electrical fields.

    摘要翻译: SiC的pn二极管具有掺杂有低电离能的第一掺杂剂的第一发射极层部分和被设计为栅极的第二部分,并且具有从上方垂直延伸并且穿过漂移层和第一部分之间的结的部分,并且 通过用于由第一部分形成pn结的漂移层区域和与栅极部分的下端垂直距离的这些部分相邻的漂移层横向分开。 选择器件的不同参数以允许在阻挡状态下漂移层的耗尽在栅格部分之间形成连续的耗尽区,从而屏蔽pn结处的高电场,使其不会暴露 到高电场。

    Method for producing a semiconductor device by the use of an implanting
step
    4.
    发明授权
    Method for producing a semiconductor device by the use of an implanting step 失效
    通过使用植入步骤制造半导体器件的方法

    公开(公告)号:US5674765A

    公开(公告)日:1997-10-07

    申请号:US636952

    申请日:1996-04-24

    摘要: A method for producing a semiconductor device comprising a step a) of implanting an impurity dopant of a first conductivity type into said semiconductor layer (1) being doped according to a second opposite conductivity type for forming a first type doped surface layer (2) surrounded, except for the top surface thereof, by second conductivity type doped regions (3) of said semiconductor layer for forming a pn-junction (4) at the interface thereto. A highly doped additional semiconductor layer (5) is grown on top of said surface layer (2) for forming a contact layer allowing a low resistance ohmic contact to be established to the device so created.

    摘要翻译: 一种制造半导体器件的方法,包括以下步骤a):将第一导电类型的杂质掺杂剂注入到所述半导体层(1)中,所述半导体层(1)根据第二相反导电类型掺杂以形成包围的第一类型掺杂表面层(2) ,除了其顶表面之外,通过用于在其界面处形成pn结(4)的所述半导体层的第二导电类型掺杂区(3)。 高度掺杂的附加半导体层(5)生长在所述表面层(2)的顶部上,用于形成接触层,从而允许对所产生的器件建立低电阻欧姆接触。

    SiC semiconductor device comprising a pn junction with a voltage
absorbing edge
    5.
    发明授权
    SiC semiconductor device comprising a pn junction with a voltage absorbing edge 失效
    SiC半导体器件包括具有电压吸收边缘的pn结

    公开(公告)号:US6002159A

    公开(公告)日:1999-12-14

    申请号:US683059

    申请日:1996-07-16

    摘要: A semiconductor component including a silicon carbide substrate. A pn junction includes doped layers of the substrate. The pn junction includes at a surface of the substrate a low doped first conductivity type layer and at a portion of the surface of the substrate a highly doped second conductivity type layer. An edge termination region of the pn junction laterally surrounds the pn junction provided at an edge of at least one of the layers of the pn junction. The edge termination region includes zones of the second conductivity type located at an edge of the highly doped second conductivity type layer. A charge content of the zones decreases toward an edge of the edge termination region in accordance with at least one characteristic selected from the group consisting of a stepwise or continuously decreasing total charge towards an outer border of the edge termination region and a decreasing effective sheet charge density toward an outer border of the edge termination region. An outermost zone of the edge termination region is completely depleted at full design voltage.

    摘要翻译: 包括碳化硅衬底的半导体部件。 pn结包括衬底的掺杂层。 pn结在衬底的表面上包括低掺杂的第一导电类型层,并且在衬底的表面的一部分处包括高度掺杂的第二导电类型层。 pn结的边缘终止区横向地围绕设置在pn结的至少一个层的边缘处的pn结。 边缘终止区域包括位于高度掺杂的第二导电类型层的边缘处的第二导电类型的区域。 根据从边缘终止区域的外边界逐步或连续减小的总电荷和降低的有效片材电荷的组中选出的至少一个特征,区域的电荷含量朝向边缘终止区域的边缘减小 密度朝向边缘终止区域的外边界。 边缘终端区域的最外区域在完全设计电压下完全耗尽。

    Method for producing a semiconductor device having a semiconductor layer
of SiC by implanting
    6.
    发明授权
    Method for producing a semiconductor device having a semiconductor layer of SiC by implanting 失效
    通过注入制造具有SiC半导体层的半导体器件的方法

    公开(公告)号:US5710059A

    公开(公告)日:1998-01-20

    申请号:US636942

    申请日:1996-04-24

    申请人: Kurt Rottner

    发明人: Kurt Rottner

    IPC分类号: H01L21/04 H01L21/22

    CPC分类号: H01L29/6606 H01L21/046

    摘要: A method for producing a semiconductor device comprises a step of implanting first conductivity type impurity dopants of at least two different elements in a semiconductor layer being doped according to a second opposite conductivity type, and after that anneal the semiconductor layer at such a high temperature that one of said elements is diffusing slowly into the semiconductor layer and the other is diffusing rapidly thereinto.

    摘要翻译: 一种制造半导体器件的方法包括在根据第二相反导电类型掺杂的半导体层中注入至少两种不同元素的第一导电型杂质掺杂剂的步骤,并且在半导体层退火之后, 所述元件中的一个缓慢地扩散到半导体层中,另一个在其中快速扩散。

    Method for producing a region doped with boron in a SiC-layer
    7.
    发明授权
    Method for producing a region doped with boron in a SiC-layer 失效
    在SiC层中制造掺杂有硼的区域的方法

    公开(公告)号:US06703294B1

    公开(公告)日:2004-03-09

    申请号:US08735389

    申请日:1996-10-21

    IPC分类号: H01L21265

    摘要: A method for producing a crystalline layer of SiC having at least a region thereof doped with boron atoms comprises a step a) of ion implantation of boron into a layer (1) of crystalline SiC and a step b) of heating the SiC-layer for annealing it for making the boron implanted therein electrically active. The method further comprises a step c) of implanting carbon atoms in said layer (1) for forming carbon interstitials in excess with respect to carbon vacancies present in the SiC-layer before carrying out step b).

    摘要翻译: 一种制造具有至少其掺杂有硼原子的区域的SiC的结晶层的方法包括将硼离子注入到结晶SiC的层(1)中的步骤a)和步骤b)将SiC层加热 对其进行退火以使其中注入的硼具有电活性。 该方法还包括在执行步骤b)之前,将碳原子注入所述层(1)中以形成相对于存在于SiC层中的碳空位过剩的碳间隙的步骤c)。

    Circuit coupling an oscillator to an electrical load
    8.
    发明授权
    Circuit coupling an oscillator to an electrical load 失效
    电路耦合振荡器到电力负载

    公开(公告)号:US5053727A

    公开(公告)日:1991-10-01

    申请号:US512469

    申请日:1990-04-23

    IPC分类号: H02M3/28 H02M3/338 H03B5/06

    CPC分类号: H02M3/3381

    摘要: A circuit comprising an oscillator having a load coupled thereto by means of at least one voltage-dependent coupling element that exhibits a high impedance at relatively low voltages and low impedance at relatively higher voltages. The voltage-dependent coupling element can comprise two series connected Zener diodes connected such that the anodes of the diodes are coupled together. The voltage-dependent coupling element can also comprise a varistor.

    摘要翻译: 一种电路,包括通过至少一个电压相关耦合元件耦合到其上的负载的振荡器,所述至少一个电压相关耦合元件在相对低的电压下呈现高阻抗,并且在较高电压下呈现低阻抗。 电压依赖耦合元件可以包括两个连接的串联连接的齐纳二极管,使得二极管的阳极耦合在一起。 电压依赖耦合元件还可以包括变阻器。

    Method for producing a semiconductor device comprising an implantation
step
    10.
    发明授权
    Method for producing a semiconductor device comprising an implantation step 失效
    一种用于制造包括注入步骤的半导体器件的方法

    公开(公告)号:US5849620A

    公开(公告)日:1998-12-15

    申请号:US544979

    申请日:1995-10-30

    IPC分类号: H01L21/04 H01L21/265

    CPC分类号: H01L29/66068 H01L21/046

    摘要: A method for producing a semiconductor device having a semiconductor layer of SiC is disclosed. The method comprises the steps of applying an insulation layer on the semiconductor layer, implanting first impurity dopant into the semiconductor layer, and annealing this layer at at least about 1500.degree. C. so that the implanted first impurity dopant is activated, wherein the insulating layer comprises AlN as a major component and the insulating layer is applied before the annealing step and maintained on the semiconductor layer during the annealing step.

    摘要翻译: 公开了一种制造具有SiC半导体层的半导体器件的方法。 该方法包括以下步骤:在半导体层上施加绝缘层,将第一杂质掺杂剂注入到半导体层中,并在至少约1500℃对该层进行退火,使得注入的第一杂质掺杂剂被激活,其中绝缘层 包括AlN作为主要成分,并且在退火步骤之前施加绝缘层,并且在退火步骤期间保持在半导体层上。