公开(公告)号：US20110181328A1

公开(公告)日：2011-07-28

申请号：US13083247

申请日：2011-04-08

申请人： Kwang Jun CHO ,  Jun Hyun Chun

发明人： Kwang Jun CHO ,  Jun Hyun Chun

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

摘要翻译： 一种频率调整装置，包括：频率控制信号生成部，其响应于基准时钟信号，生成逐位变化的多位频率控制信号;以及频率调整部，其调整基准的频率 响应于多位频率控制信号的时钟信号。

公开(公告)号：US08253459B2

公开(公告)日：2012-08-28

申请号：US13083247

申请日：2011-04-08

申请人： Kwang Jun Cho ,  Jun Hyun Chun

发明人： Kwang Jun Cho ,  Jun Hyun Chun

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

摘要翻译： 一种频率调整装置，包括：频率控制信号生成部，其响应于基准时钟信号，生成逐位变化的多位频率控制信号;以及频率调整部，其调整基准的频率 响应于多位频率控制信号的时钟信号。

公开(公告)号：US20080315927A1

公开(公告)日：2008-12-25

申请号：US11966300

申请日：2007-12-28

申请人： Kwang Jun Cho ,  Jun Hyun Chun

发明人： Kwang Jun Cho ,  Jun Hyun Chun

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

摘要翻译： 一种频率调整装置，包括：频率控制信号生成部，其响应于基准时钟信号，生成逐位变化的多位频率控制信号;以及频率调整部，其调整基准的频率 响应于多位频率控制信号的时钟信号。

公开(公告)号：US07537942B2

公开(公告)日：2009-05-26

申请号：US11685870

申请日：2007-03-14

申请人： Kang Youl Lee ,  Jun Hyun Chun

发明人： Kang Youl Lee ,  Jun Hyun Chun

IPC分类号： H01L21/66

CPC分类号： H03K19/017581

摘要： Provided is a method of changing an output current value of an off-chip driver by means of a counting circuit including pluralities of fuses for controlling the off-chip driver, that includes measuring the output current value of the off-chip driver after completing a wafer test; cutting the fuses of the counting circuit off when the measured output current value is smaller than a target value, increasing the initial value of a off-chip driving control signal; and fabricating a package when the measured output current value is equal to a target value.

摘要翻译： 提供了一种通过包括用于控制片外驱动器的多个保险丝的计数电路来改变片外驱动器的输出电流值的方法，其包括在完成了片外驱动器之后测量片外驱动器的输出电流值 晶圆试验; 当测量的输出电流值小于目标值时，切断计数电路的熔丝，增加芯片外驱动控制信号的初始值; 以及当测量的输出电流值等于目标值时制造封装。

公开(公告)号：US06643218B1

公开(公告)日：2003-11-04

申请号：US10347276

申请日：2003-01-21

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： G11C800

CPC分类号： G11C7/12

摘要： A semiconductor memory device generates a precharge control signal asynchronous from a dock signal. The semiconductor memory device includes a memory cell array for storing data, and a precharge control signal generator for generating a precharge control signal in a test mode, by employing a predetermined control signal which does not influence access to the data stored in the memory cell array, even when maintained in a high or low level in the test mode. The precharge control signal generator receives the control signal, outputs a signal having an identical state to the control signal in the normal mode, and also outputs a signal fixed in a high or low level in the test mode. As a result, it is possible to generate the precharge control signal which does not require a delay time as long as a command hold time.

摘要翻译： 半导体存储器件从停靠信号产生异步的预充电控制信号。 半导体存储器件包括用于存储数据的存储单元阵列和预充电控制信号发生器，用于通过采用不影响对存储在存储单元阵列中的数据的访问的预定控制信号来产生测试模式中的预充电控制信号 即使在测试模式下保持在高或低电平。 预充电控制信号发生器接收控制信号，在正常模式下输出与控制信号具有相同状态的信号，并且还在测试模式下输出固定在高电平或低电平的信号。 结果，可以产生不需要延迟时间的预充电控制信号，只要指令保持时间即可。

公开(公告)号：US06532184B2

公开(公告)日：2003-03-11

申请号：US09994652

申请日：2001-11-28

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： G11C700

CPC分类号： G11C7/12

摘要： A semiconductor memory device generates a precharge control signal asynchronous from a clock signal. The semiconductor memory device includes a memory cell array for storing data, and a precharge control signal generator for generating a precharge control signal in a test mode, by employing a predetermined control signal which does not influence access to the data stored in the memory cell array, even when maintained in a high or low level in the test mode. The precharge control signal generator receives the control signal, outputs a signal having an identical state to the control signal in the normal mode, and also outputs a signal fixed in a high or low level in the test mode. As a result, it is possible to generate the precharge control signal which does not require a delay time as long as a command hold time.

公开(公告)号：US20090122625A1

公开(公告)日：2009-05-14

申请号：US12172949

申请日：2008-07-14

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G11C29/48

摘要： A semiconductor memory device including a test circuit capable of reducing test time includes a test circuit for generating leakage current in the semiconductor memory device in a standby state in response to a test mode signal and a standby signal that provides standby state information of the semiconductor memory device.

摘要翻译： 包括能够减少测试时间的测试电路的半导体存储器件包括用于响应于测试模式信号和提供半导体存储器的备用状态信息的待机信号在待机状态下产生半导体存储器件中的漏电流的测试电路 设备。

公开(公告)号：US07142467B2

公开(公告)日：2006-11-28

申请号：US11004842

申请日：2004-12-07

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/22 ,  G11C7/225

摘要： A synchronous semiconductor memory device reduces operation current by limiting unnecessary internal operations with a command interval defined in the JEDEC Standard. The synchronous semiconductor memory device comprises a clock buffer, a plurality of command buffers, a plurality of address buffers, a command decoder, a clock driving unit, and a plurality of address latches. Here, the command decoder generates an internal command in response to output signals from the plurality of command buffers synchronously with respect to an internal clock. The clock driving unit drives a clock outputted from the clock buffer to generate the internal clock, and generates a latch clock that toggles only when the internal command is generated. The plurality of address latches generates a plurality of latch addresses in response to a plurality of internal addresses outputted from the plurality of address buffers synchronously with respect to the latch clock.

摘要翻译： 同步半导体存储器件通过使用JEDEC标准中定义的命令间隔来限制不必要的内部操作来减少操作电流。 同步半导体存储器件包括时钟缓冲器，多个命令缓冲器，多个地址缓冲器，命令解码器，时钟驱动单元和多个地址锁存器。 这里，命令解码器响应于来自多个命令缓冲器的输出信号，相对于内部时钟同步地产生内部命令。 时钟驱动单元驱动从时钟缓冲器输出的时钟以产生内部时钟，并且产生仅在产生内部命令时切换的锁存时钟。 响应于从锁存时钟同步地从多个地址缓冲器输出的多个内部地址，多个地址锁存器产生多个锁存地址。

公开(公告)号：US08908778B2

公开(公告)日：2014-12-09

申请号：US13590282

申请日：2012-08-21

申请人： Jin Il Chung ,  Jun Hyun Chun ,  Jin Wook Burm ,  Dae Ho Yun

发明人： Jin Il Chung ,  Jun Hyun Chun ,  Jin Wook Burm ,  Dae Ho Yun

IPC分类号： H04B14/06

CPC分类号： H03K5/249 ,  H04L25/4917 ,  H04L27/06

摘要： A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

摘要翻译： 一种轨到轨比较器，包括连接到第一端子并被配置为将差分输入信号与差分参考电压进行比较的第一比较单元; 第二比较单元，连接到第二端子并且被配置为将差分输入信号与差分参考电压进行比较; 以及输出单元，被配置为响应于时钟信号被驱动，并且根据第一和第二比较单元的比较结果产生互补的输出信号。

公开(公告)号：US5764652A

公开(公告)日：1998-06-09

申请号：US723244

申请日：1996-09-30

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： H01L21/82 ,  G11C29/00 ,  G11C29/04 ,  G11C29/18 ,  G06F11/00

CPC分类号： G11C29/842

摘要： A repair circuit of a semiconductor memory device is disclosed, including an address input unit for receiving and processing external addresses; a repair detecting unit for detecting whether there are addresses repaired on a programmed data basis; a normal decoding unit for selecting normal word lines; a redundant decoding unit for selecting redundant word lines; a repair address determining unit, enabled by a signal produced from the repair detecting unit, for comparing the external addresses with repair addresses programmed therein; a normal decoder control unit for controlling a turned-on or turned-off state of the normal decoding unit by receiving the external addresses, the signal produced from the repair detecting unit, and a repair signal produced from the repair address determining unit; an address delay unit for controlling delays of the external addresses, based on the output signals of the repair detecting unit; and a sense amplifier control unit driven by an output signal from the address delay unit.

摘要翻译： 公开了一种半导体存储器件的修复电路，包括用于接收和处理外部地址的地址输入单元; 修复检测单元，用于检测是否存在以编程数据为基础修复的地址; 用于选择正常字线的正常解码单元; 用于选择冗余字线的冗余解码单元; 修复地址确定单元，由修复检测单元产生的信号使能，用于将外部地址与其中编程的维修地址进行比较; 正常解码器控制单元，用于通过接收外部地址，从修复检测单元产生的信号和从修复地址确定单元产生的修复信号来控制正常解码单元的导通或关闭状态; 地址延迟单元，用于根据修复检测单元的输出信号来控制外部地址的延迟; 以及由来自地址延迟单元的输出信号驱动的读出放大器控制单元。