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    NAND-type flash memory devices and methods of fabricating the same
    1.
    发明授权
    NAND-type flash memory devices and methods of fabricating the same 有权
    NAND型闪存器件及其制造方法

    公开(公告)号：US06376876B1

    公开(公告)日：2002-04-23

    申请号：US09678917

    申请日：2000-10-04

    申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

    发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

    IPC分类号： H01L2978

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

    摘要翻译： 提供了NAND​​型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。 该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。 源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。 源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

    NAND-type flash memory devices and methods of fabricating the same
    2.
    发明申请
    NAND-type flash memory devices and methods of fabricating the same 有权
    NAND型闪存器件及其制造方法

    公开(公告)号：US20050023600A1

    公开(公告)日：2005-02-03

    申请号：US10921656

    申请日：2004-08-19

    申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

    发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

    IPC分类号： H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  H01L21/76802 ,  H01L27/115 ,  H01L27/11524

    摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

    摘要翻译： 提供了NAND​​型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。 该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。 源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。 源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

    NAND-type flash memory devices and methods of fabricating the same
    4.
    发明授权
    NAND-type flash memory devices and methods of fabricating the same 有权
    NAND型闪存器件及其制造方法

    公开(公告)号：US06797570B2

    公开(公告)日：2004-09-28

    申请号：US10087330

    申请日：2002-03-01

    申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

    发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

    IPC分类号： H01L21336

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

    摘要翻译： 提供了NAND​​型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。 该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。 源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。 源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

    Method of fabricating cell of nonvolatile memory device with floating gate
    5.
    发明授权
    Method of fabricating cell of nonvolatile memory device with floating gate 有权
    具有浮动栅极的非易失性存储器件单元制造方法

    公开(公告)号：US07449763B2

    公开(公告)日：2008-11-11

    申请号：US11530827

    申请日：2006-09-11

    申请人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

    发明人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

    IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

    摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

    摘要翻译： 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

    Method of fabricating cell of nonvolatile memory device with floating gate
    6.
    发明授权
    Method of fabricating cell of nonvolatile memory device with floating gate 有权
    具有浮动栅极的非易失性存储器件单元制造方法

    公开(公告)号：US07122426B2

    公开(公告)日：2006-10-17

    申请号：US10788002

    申请日：2004-02-25

    申请人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

    发明人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

    摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

    摘要翻译： 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

    Cells of nonvolatile memory device with high inter-layer dielectric constant
    7.
    发明授权
    Cells of nonvolatile memory device with high inter-layer dielectric constant 有权
    具有高层间介电常数的非易失性存储器件的单元

    公开(公告)号：US06903406B2

    公开(公告)日：2005-06-07

    申请号：US10346957

    申请日：2003-01-17

    申请人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

    发明人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

    摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

    摘要翻译： 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。