公开(公告)号：US08383477B2

公开(公告)日：2013-02-26

申请号：US12976792

申请日：2010-12-22

Applicant: Kyoung Han Lee

Inventor： Kyoung Han Lee

IPC: H01L21/8238 ,  H01L21/8242

CPC classification number: H01L27/105 ,  H01L27/108 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L28/40 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor disposed over the upper portion of the active region and the word line.

Abstract translation: 包括垂直晶体管的半导体器件及其制造方法可以减小与8F2和6F2的常规布局相比的单元面积。 此外，该方法不需要形成位线接触，存储节点接触或着陆塞，从而减少处理步骤。 包括垂直晶体管的半导体器件包括：形成在半导体衬底中的有源区; 位于有源区的下部的位线; 埋在活跃区域的字线; 以及设置在有源区域和字线的上部上方的电容器。