公开(公告)号：US20080211980A1

公开(公告)日：2008-09-04

申请号：US12005904

申请日：2007-12-27

申请人： Kyoung-Ju Shin ,  Shi-Yul Kim ,  Hye-Young Ryu ,  Mee-Hye Jung ,  Jang-Soo Kim ,  Su-Hyoung Kang

发明人： Kyoung-Ju Shin ,  Shi-Yul Kim ,  Hye-Young Ryu ,  Mee-Hye Jung ,  Jang-Soo Kim ,  Su-Hyoung Kang

IPC分类号： G02F1/1343 ,  H01L29/04

CPC分类号： G02F1/136209 ,  G02F1/133512 ,  G02F1/133707 ,  G02F1/136286 ,  G02F2001/136222

摘要： A display substrate includes a gate line, a gate insulating layer, a data line, a thin-film transistor (TFT), a storage line, a passivation layer, a color filter layer, a pixel electrode, a first light-blocking layer and a second light-blocking layer. The storage line includes the same material as the gate line. The passivation layer covers the data line. The color filter layer is formed on the passivation layer. The pixel electrode is formed on the color filter layer in each pixel. The first light-blocking layer is formed between adjacent pixel electrodes, and includes the same material as the gate line. The second light-blocking layer is formed between the first light-blocking layer, and includes the same material as the data line. Therefore, an aperture ratio may be increased.

摘要翻译： 显示基板包括栅极线，栅极绝缘层，数据线，薄膜晶体管（TFT），存储线，钝化层，滤色器层，像素电极，第一遮光层和 第二遮光层。 存储线包括与栅极线相同的材料。 钝化层覆盖数据线。 滤色层在钝化层上形成。 像素电极形成在每个像素中的滤色器层上。 第一遮光层形成在相邻的像素电极之间，并且包括与栅极线相同的材料。 第二遮光层形成在第一遮光层之间，并且包括与数据线相同的材料。 因此，可以增加开口率。

公开(公告)号：US08013945B2

公开(公告)日：2011-09-06

申请号：US12005904

申请日：2007-12-27

申请人： Kyoung-Ju Shin ,  Shi-Yul Kim ,  Hye-Young Ryu ,  Mee-Hye Jung ,  Jang-Soo Kim ,  Su-Hyoung Kang

发明人： Kyoung-Ju Shin ,  Shi-Yul Kim ,  Hye-Young Ryu ,  Mee-Hye Jung ,  Jang-Soo Kim ,  Su-Hyoung Kang

IPC分类号： G02F1/1343 ,  H01L29/04

CPC分类号： G02F1/136209 ,  G02F1/133512 ,  G02F1/133707 ,  G02F1/136286 ,  G02F2001/136222

摘要： A display substrate includes a gate line, a gate insulating layer, a data line, a thin-film transistor (TFT), a storage line, a passivation layer, a color filter layer, a pixel electrode, a first light-blocking layer and a second light-blocking layer. The storage line includes the same material as the gate line. The passivation layer covers the data line. The color filter layer is formed on the passivation layer. The pixel electrode is formed on the color filter layer in each pixel. The first light-blocking layer is formed between adjacent pixel electrodes, and includes the same material as the gate line. The second light-blocking layer is formed between the first light-blocking layer, and includes the same material as the data line. Therefore, an aperture ratio may be increased.

摘要翻译： 显示基板包括栅极线，栅极绝缘层，数据线，薄膜晶体管（TFT），存储线，钝化层，滤色器层，像素电极，第一遮光层和 第二遮光层。 存储线包括与栅极线相同的材料。 钝化层覆盖数据线。 滤色层在钝化层上形成。 像素电极形成在每个像素中的滤色器层上。 第一遮光层形成在相邻的像素电极之间，并且包括与栅极线相同的材料。 第二遮光层形成在第一遮光层之间，并且包括与数据线相同的材料。 因此，可以增加开口率。

公开(公告)号：US20080001937A1

公开(公告)日：2008-01-03

申请号：US11759515

申请日：2007-06-07

申请人： Kyoung-Ju Shin ,  Jin-Ho Ju ,  Shi-Yul Kim ,  Jang-Soo Kim ,  Chong-Chul Chai ,  Hye-Young Ryu

发明人： Kyoung-Ju Shin ,  Jin-Ho Ju ,  Shi-Yul Kim ,  Jang-Soo Kim ,  Chong-Chul Chai ,  Hye-Young Ryu

IPC分类号： G09G5/00

CPC分类号： G02F1/136227 ,  G02F2001/136222 ,  H01L27/1248

摘要： A display substrate includes a TFT layer, a passivation layer, an organic layer, an inorganic insulating layer and a pixel electrode. The TFT layer includes gate and data lines, a thin film transistor and a storage electrode. The data line crosses the gate line, and is electrically insulated from the gate line by a gate insulating layer. The TFT is electrically connected to the gate and data lines. The passivation layer covers the TFT layer. The organic layer is on the passivation layer. The inorganic insulating layer of a low temperature deposition is on the organic layer, and the low temperature is about 100° C. to about 250° C. The pixel electrode is on the inorganic insulating layer to be electrically connected to the TFT through a contact hole that is formed through the inorganic insulating layer, the organic layer and the passivation layer. The inorganic insulating layer helps to block leakage of impurities from the organic layer to layers above the inorganic insulating layer.

摘要翻译： 显示基板包括TFT层，钝化层，有机层，无机绝缘层和像素电极。 TFT层包括栅极和数据线，薄膜晶体管和存储电极。 数据线与栅极线交叉，并通过栅极绝缘层与栅极线电绝缘。 TFT与栅极和数据线电连接。 钝化层覆盖TFT层。 有机层位于钝化层上。 低温沉积的无机绝缘层在有机层上，低温约为100℃至约250℃。像素电极位于无机绝缘层上，通过接触电连接到TFT 通过无机绝缘层，有机层和钝化层形成的孔。 无机绝缘层有助于阻止杂质从有机层泄漏到无机绝缘层上方的层。

公开(公告)号：US20100203715A1

公开(公告)日：2010-08-12

申请号：US12765698

申请日：2010-04-22

申请人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L21/28

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US20080203393A1

公开(公告)日：2008-08-28

申请号：US12099718

申请日：2008-04-08

申请人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab KIM ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L27/088

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US08305507B2

公开(公告)日：2012-11-06

申请号：US11356853

申请日：2006-02-17

申请人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

发明人： Hye-Young Ryu ,  Jang-Soo Kim ,  Sang-Gab Kim ,  Hong-Kee Chin ,  Min-Seok Oh ,  Hee-Hwan Choe ,  Shi-Yul Kim

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/133345 ,  G02F1/1362 ,  G02F2001/136222 ,  G02F2202/02

摘要： A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括栅极线，与栅极线相交的数据线，与栅极和数据线分开的存储电极，连接到栅极和数据线并具有漏极的薄膜晶体管 连接到漏电极的像素电极，薄膜晶体管上的第一绝缘层，并且设置在像素电极下方;第二绝缘层，设置在第一绝缘层上，并且具有使存储电极上的第一绝缘层露出的开口 。

公开(公告)号：US08173493B2

公开(公告)日：2012-05-08

申请号：US12765698

申请日：2010-04-22

申请人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US20080252828A1

公开(公告)日：2008-10-16

申请号：US11930653

申请日：2007-10-31

申请人： Kyoung-Ju Shin ,  Hye-Young Ryu ,  Jang-Soo Kim ,  Chong-Chul Chal ,  Jae-Hyoung Youn ,  Young-Wook Lee

发明人： Kyoung-Ju Shin ,  Hye-Young Ryu ,  Jang-Soo Kim ,  Chong-Chul Chal ,  Jae-Hyoung Youn ,  Young-Wook Lee

IPC分类号： G02F1/1335 ,  G02F1/1343

CPC分类号： G02F1/133514 ,  G02F1/134309 ,  G02F2001/134345 ,  G02F2001/136222

摘要： A thin film transistor array panel includes a substrate, a first gate line and a second gate line formed on the substrate, a storage electrode line between the first gate line and the second gate line, a data line intersecting the first gate line and the second gate line, a first thin film transistor connected to the first gate line and the data line, at least one color filter formed on the first thin film transistor, wherein the color filter comprises a first portion adjacent the first gate line with respect to the storage electrode line, a second portion adjacent the second gate line with respect to the storage electrode line, and a first connection connecting the first portion and the second portion and having a narrower width than that of the first and second portions, a first sub-pixel electrode formed on the color filter and connected to the first thin film transistor, and a second sub-pixel electrode facing the first sub-pixel electrode with respect to a gap, wherein at least one of an edge of the first sub-pixel electrode and an edge of the second sub-pixel electrode crosses over the first connection of the color filter, the edge of the first sub-pixel electrode, and the edge of the second sub-pixel electrode defining the gap between the first sub-pixel electrode and the second sub-pixel electrode.

摘要翻译： 薄膜晶体管阵列面板包括基板，形成在基板上的第一栅极线和第二栅极线，在第一栅极线和第二栅极线之间的存储电极线，与第一栅极线和第二栅极线相交的数据线 栅极线，连接到第一栅极线和数据线的第一薄膜晶体管，形成在第一薄膜晶体管上的至少一个滤色器，其中滤色器包括相对于存储器的第一栅极线的第一部分 电极线，相对于存储电极线相邻于第二栅极线的第二部分，以及连接第一部分和第二部分并且具有比第一和第二部分窄的宽度的第一连接，第一子像素 电极，形成在滤色器上并连接到第一薄膜晶体管，第二子像素电极相对于间隙面对第一子像素电极，其中至少在 第一子像素电极的边缘和第二子像素电极的边缘的第二子像素电极的边缘与滤色器的第一连接，第一子像素电极的边缘和第二子像素电极的边缘交叉 限定第一子像素电极和第二子像素电极之间的间隙的电极。

公开(公告)号：US08604478B2

公开(公告)日：2013-12-10

申请号：US13168769

申请日：2011-06-24

申请人： Hye-Young Ryu ,  Jang-Soo Kim ,  Su-Hyoung Kang

发明人： Hye-Young Ryu ,  Jang-Soo Kim ,  Su-Hyoung Kang

IPC分类号： H01L29/04

CPC分类号： G02F1/136227 ,  G02F2001/136222 ,  H01L27/3258

摘要： In a thin-film transistor (TFT) substrate, a gate insulating layer is disposed on a gate electrode electrically connected to a gate line. A semiconductor layer is disposed on the gate insulating layer. A source electrode is electrically connected to a data line that intersects the gate line. A drain electrode faces the source electrode and defines a channel area of a semiconductor layer. An organic layer is disposed on the data line and has a first opening exposing the channel area. An inorganic insulating layer is disposed on the organic layer. A pixel electrode is disposed on the inorganic insulating layer and electrically connected to the drain electrode. The inorganic insulating layer covers the first opening, and thickness of the inorganic insulating layer is substantially uniform.

摘要翻译： 在薄膜晶体管（TFT）基板中，栅极绝缘层设置在与栅极线电连接的栅电极上。 半导体层设置在栅极绝缘层上。 源极电极与与栅极线相交的数据线电连接。 漏电极面对源电极并限定半导体层的沟道面积。 有机层设置在数据线上，并且具有暴露通道区域的第一开口。 无机绝缘层设置在有机层上。 像素电极设置在无机绝缘层上并与漏电极电连接。 无机绝缘层覆盖第一开口，无机绝缘层的厚度基本均匀。

公开(公告)号：US07888675B2

公开(公告)日：2011-02-15

申请号：US12099718

申请日：2008-04-08

申请人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

发明人： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  G02F2001/13629 ,  H01L29/458

摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

摘要翻译： 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。