公开(公告)号：US20100073023A1

公开(公告)日：2010-03-25

申请号：US12555886

申请日：2009-09-09

申请人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

发明人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

摘要： Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

摘要翻译： 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，可以使用无源部件，有源部件或两者来实现内部阻抗。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

公开(公告)号：US20120081146A1

公开(公告)日：2012-04-05

申请号：US13316046

申请日：2011-12-09

申请人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

发明人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

IPC分类号： H03K19/003

CPC分类号： H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

摘要： Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

摘要翻译： 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，可以使用无源部件，有源部件或两者来实现内部阻抗。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

公开(公告)号：US20110128040A1

公开(公告)日：2011-06-02

申请号：US13022539

申请日：2011-02-07

申请人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

发明人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

IPC分类号： H03K19/003

CPC分类号： H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

摘要： Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

摘要翻译： 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号之后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，可以使用无源部件，有源部件或两者来实现内部阻抗。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

公开(公告)号：US08692573B2

公开(公告)日：2014-04-08

申请号：US13316046

申请日：2011-12-09

申请人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

发明人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

摘要： Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

摘要翻译： 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号之后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，可以使用无源部件，有源部件或两者来实现内部阻抗。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

公开(公告)号：US08130010B2

公开(公告)日：2012-03-06

申请号：US13022539

申请日：2011-02-07

申请人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

发明人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

摘要： Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

摘要翻译： 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号之后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，内部阻抗可以使用无源部件，有源部件或两者来实现。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

公开(公告)号：US07915912B2

公开(公告)日：2011-03-29

申请号：US12555886

申请日：2009-09-09

申请人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

发明人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

摘要： Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

摘要翻译： 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号之后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，可以使用无源部件，有源部件或两者来实现内部阻抗。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

公开(公告)号：US08378699B2

公开(公告)日：2013-02-19

申请号：US12430832

申请日：2009-04-27

申请人： Bret Stott ,  Philip Yeung ,  John W. Brooks ,  Benedict Lau ,  Chanh V. Tran ,  Eugene C. Ho

发明人： Bret Stott ,  Philip Yeung ,  John W. Brooks ,  Benedict Lau ,  Chanh V. Tran ,  Eugene C. Ho

IPC分类号： G01R31/20 ,  G01R31/26

CPC分类号： G01R31/31716 ,  G11C29/022

摘要： An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

摘要翻译： 描述了集成电路。 集成电路包括包括发射机和接收机的接口电路。 集成电路中的发生器选择性地耦合到发射机。 发生器将提供在测试操作模式期间由发射器输出的测试序列。 集成电路中的存储器选择性地耦合到发生器和接收器。 存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。 集成电路中的逻辑电路是比较测试序列和信号。

公开(公告)号：US20090206867A1

公开(公告)日：2009-08-20

申请号：US12430832

申请日：2009-04-27

申请人： Bret Stott ,  Philip Yeung ,  John W. Brooks ,  Benedict Lau ,  Chanh V. Tran ,  Eugene C. Ho

发明人： Bret Stott ,  Philip Yeung ,  John W. Brooks ,  Benedict Lau ,  Chanh V. Tran ,  Eugene C. Ho

IPC分类号： G01R31/26

CPC分类号： G01R31/31716 ,  G11C29/022

摘要： An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

摘要翻译： 描述了集成电路。 集成电路包括包括发射机和接收机的接口电路。 集成电路中的发生器选择性地耦合到发射机。 发电机将提供在测试操作模式期间由发射机输出的测试序列。 集成电路中的存储器选择性地耦合到发生器和接收器。 存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。 集成电路中的逻辑电路是比较测试序列和信号。

公开(公告)号：US07535242B2

公开(公告)日：2009-05-19

申请号：US11417964

申请日：2006-05-03

申请人： Bret Stott ,  Philip Yeung ,  John W. Brooks ,  Benedict Lau ,  Chanh V. Tran ,  Eugene C. Ho

发明人： Bret Stott ,  Philip Yeung ,  John W. Brooks ,  Benedict Lau ,  Chanh V. Tran ,  Eugene C. Ho

IPC分类号： G01R31/26

CPC分类号： G01R31/31716 ,  G11C29/022

摘要： An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

摘要翻译： 描述了集成电路。 集成电路包括包括发射机和接收机的接口电路。 集成电路中的发生器选择性地耦合到发射机。 发生器将提供在测试操作模式期间由发射器输出的测试序列。 集成电路中的存储器选择性地耦合到发生器和接收器。 存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。 集成电路中的逻辑电路是比较测试序列和信号。

公开(公告)号：US20100185810A1

公开(公告)日：2010-07-22

申请号：US12602673

申请日：2008-06-12

申请人： Julia K. Cline ,  Eugene C. Ho ,  Bret G. Stott ,  Frederick A. Ware

发明人： Julia K. Cline ,  Eugene C. Ho ,  Bret G. Stott ,  Frederick A. Ware

IPC分类号： G06F12/00 ,  G06F1/04

CPC分类号： G06F13/161 ,  G06F13/1689

摘要： Systems and methods are provided for in-DRAM cycle-based levelization. In a multi-rank, multi-lane memory system, an in-DRAM cycle-based levelization mechanism couples to a memory device in a rank and individually controls additive write latency and/or additive read latency for the memory device. The in-DRAM levelization mechanism ensures that a distribution of relative total write or read latencies across the lanes in the rank is substantially similar to that in another rank.

摘要翻译： 提供了用于基于DRAM循环的分级的系统和方法。 在多级多通道存储器系统中，基于DRAM周期的调平机制以等级耦合到存储器件，并且分别控制存储器件的附加写延迟和/或加性读延迟。 DRAM内级别化机制确保在等级中的通道上的相对总写入或读取延迟的分布基本上类似于另一个等级。