公开(公告)号：US07501655B2

公开(公告)日：2009-03-10

申请号：US11749426

申请日：2007-05-16

申请人： Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

发明人： Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136218 ,  G02F2001/136222 ,  H01L27/1214 ,  H01L27/1288

摘要： A thin film array panel is provided, which includes: a gate line formed on a substrate; a first insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed on the gate insulating layer and intersecting the gate line; a drain electrode formed at least on the semiconductor layer; a conductor arranged in parallel to the data line; a second insulating layer formed on the data line, the drain electrode, and the conductor and having a first contact hole exposing a portion of the drain electrode; and a pixel electrode formed on the second insulating layer, connected to the drain electrode through the first contact hole, fully covering the data line.

摘要翻译： 提供薄膜阵列面板，其包括：形成在基板上的栅极线; 形成在栅极线上的第一绝缘层; 形成在所述栅极绝缘层上的半导体层; 形成在栅极绝缘层上并与栅极线相交的数据线; 至少形成在所述半导体层上的漏电极; 与数据线平行布置的导体; 形成在所述数据线上的第二绝缘层，所述漏电极和所述导体，并且具有暴露所述漏电极的一部分的第一接触孔; 以及形成在第二绝缘层上的像素电极，通过第一接触孔连接到漏电极，完全覆盖数据线。

公开(公告)号：US07223997B2

公开(公告)日：2007-05-29

申请号：US11008720

申请日：2004-12-08

申请人： Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

发明人： Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136218 ,  G02F2001/136222 ,  H01L27/1214 ,  H01L27/1288

摘要： A thin film array panel is provided, which includes: a gate line formed on a substrate; a first insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed on the gate insulating layer and intersecting the gate line; a drain electrode formed at least on the semiconductor layer; a conductor arranged in parallel to the data line; a second insulating layer formed on the data line, the drain electrode, and the conductor and having a first contact hole exposing a portion of the drain electrode; and a pixel electrode formed on the second insulating layer, connected to the drain electrode through the first contact hole, fully covering the data line.

摘要翻译： 提供薄膜阵列面板，其包括：形成在基板上的栅极线; 形成在栅极线上的第一绝缘层; 形成在所述栅极绝缘层上的半导体层; 形成在栅极绝缘层上并与栅极线相交的数据线; 至少形成在所述半导体层上的漏电极; 与数据线平行布置的导体; 形成在所述数据线上的第二绝缘层，所述漏电极和所述导体，并且具有暴露所述漏电极的一部分的第一接触孔; 以及形成在第二绝缘层上的像素电极，通过第一接触孔连接到漏电极，完全覆盖数据线。

公开(公告)号：US20050162580A1

公开(公告)日：2005-07-28

申请号：US11008720

申请日：2004-12-08

申请人： Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

发明人： Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

IPC分类号： G02F1/1333 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/786

CPC分类号： H01L27/124 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136218 ,  G02F2001/136222 ,  H01L27/1214 ,  H01L27/1288

摘要： A thin film array panel is provided, which includes: a gate line formed on a substrate; a first insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed on the gate insulating layer and intersecting the gate line; a drain electrode formed at least on the semiconductor layer; a conductor arranged in parallel to the data line; a second insulating layer formed on the data line, the drain electrode, and the conductor and having a first contact hole exposing a portion of the drain electrode; and a pixel electrode formed on the second insulating layer, connected to the drain electrode through the first contact hole, fully covering the data line.

摘要翻译： 提供薄膜阵列面板，其包括：形成在基板上的栅极线; 形成在栅极线上的第一绝缘层; 形成在所述栅极绝缘层上的半导体层; 形成在栅极绝缘层上并与栅极线相交的数据线; 至少形成在所述半导体层上的漏电极; 与数据线平行布置的导体; 形成在所述数据线上的第二绝缘层，所述漏电极和所述导体，并且具有暴露所述漏电极的一部分的第一接触孔; 以及形成在第二绝缘层上的像素电极，通过第一接触孔连接到漏电极，完全覆盖数据线。

公开(公告)号：US20070211188A1

公开(公告)日：2007-09-13

申请号：US11749426

申请日：2007-05-16

申请人： Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

发明人： Kyung-Wook Kim ,  Beom-Jun Kim ,  Sung-Man Kim ,  Byeong-Jae Ahn ,  Young-Goo Song ,  Hyang-Shik Kong

IPC分类号： G02F1/136

CPC分类号： H01L27/124 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136218 ,  G02F2001/136222 ,  H01L27/1214 ,  H01L27/1288

摘要： A thin film array panel is provided, which includes: a gate line formed on a substrate; a first insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a data line formed on the gate insulating layer and intersecting the gate line; a drain electrode formed at least on the semiconductor layer; a conductor arranged in parallel to the data line; a second insulating layer formed on the data line, the drain electrode, and the conductor and having a first contact hole exposing a portion of the drain electrode; and a pixel electrode formed on the second insulating layer, connected to the drain electrode through the first contact hole, fully covering the data line.

摘要翻译： 提供薄膜阵列面板，其包括：形成在基板上的栅极线; 形成在栅极线上的第一绝缘层; 形成在所述栅极绝缘层上的半导体层; 形成在栅极绝缘层上并与栅极线相交的数据线; 至少形成在所述半导体层上的漏电极; 与数据线平行布置的导体; 形成在所述数据线上的第二绝缘层，所述漏电极和所述导体，并且具有暴露所述漏电极的一部分的第一接触孔; 以及形成在第二绝缘层上的像素电极，通过第一接触孔连接到漏电极，完全覆盖数据线。

公开(公告)号：US07655952B2

公开(公告)日：2010-02-02

申请号：US11770012

申请日：2007-06-28

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L33/00

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge, placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并且具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US20070134858A1

公开(公告)日：2007-06-14

申请号：US11674457

申请日：2007-02-13

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L21/84

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US20050110019A1

公开(公告)日：2005-05-26

申请号：US10915958

申请日：2004-08-11

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US07190000B2

公开(公告)日：2007-03-13

申请号：US10915958

申请日：2004-08-11

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L29/04

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US07955908B2

公开(公告)日：2011-06-07

申请号：US11674457

申请日：2007-02-13

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L21/00

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。

公开(公告)号：US20080012139A1

公开(公告)日：2008-01-17

申请号：US11770012

申请日：2007-06-28

申请人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

发明人： Hye-Young Ryu ,  Young-Hoon Yoo ,  Jang-Soo Kim ,  Sung-Man Kim ,  Kyung-Wook Kim ,  Hyang-Shik Kong ,  Young-Goo Song

IPC分类号： H01L23/48

CPC分类号： G02F1/136227 ,  G02F2001/136236 ,  H01L27/1244 ,  H01L27/1248

摘要： A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge, placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：顺序地形成在基板上的栅极线，栅极绝缘层和半导体层; 至少形成在所述半导体层上的数据线和漏电极; 形成在所述数据线和所述漏电极上的第一钝化层，并且具有至少部分地暴露所述漏电极的第一接触孔; 第二钝化层，其形成在所述第一钝化层上，并且具有设置在所述第一接触孔上并且具有放置在所述第一接触孔外部的第一底部边缘的第二接触孔和放置在所述第一接触孔内部的第二底部边缘; 以及形成在所述第二钝化层上并通过所述第一和第二接触孔连接到所述漏电极的像素电极。