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公开(公告)号:US08563371B2
公开(公告)日:2013-10-22
申请号:US13216051
申请日:2011-08-23
申请人: Kyung-Yub Jeon , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
发明人: Kyung-Yub Jeon , Kyoung-Sub Shin , Jun-Ho Yoon , Je-Woo Han
IPC分类号: H01L21/84 , H01L21/00 , H01L21/8238 , H01L21/461 , H01L21/302
CPC分类号: H01L21/28273 , H01L21/823456 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要: Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate.
摘要翻译: 提供一种形成半导体器件的方法。 该方法可以包括在半导体衬底上形成第一绝缘层。 可以在第一绝缘层上形成第一多晶硅层。 可以在第一多晶硅层上形成第二绝缘层。 可以在第二绝缘层上形成第二多晶硅层。 可以在第二多晶硅层上形成掩模图案。 可以使用掩模图案作为蚀刻掩模来图案化第二多晶硅层,以形成露出第二绝缘层的一部分的第二多晶硅图案。 第二多晶硅图案的侧壁可以包括第一非晶区域。 第一非晶区域可以通过第一次重结晶过程结晶。 可以去除第二绝缘层的暴露部分以形成露出第一多晶硅层的一部分的第二绝缘图案。 可以去除第一多晶硅层的暴露部分以形成露出第一绝缘层的一部分的第一多晶硅图案。 可以去除第一绝缘层的暴露部分以形成露出半导体衬底的一部分的第一绝缘图案。
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公开(公告)号:US08029688B2
公开(公告)日:2011-10-04
申请号:US12217784
申请日:2008-07-09
申请人: Shi-Yong Yi , Myeong-Cheol Kim , Dong-Ki Yoon , Kyung-Yub Jeon , Ji-Hoon Cha
发明人: Shi-Yong Yi , Myeong-Cheol Kim , Dong-Ki Yoon , Kyung-Yub Jeon , Ji-Hoon Cha
CPC分类号: H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/312 , H01L21/32139
摘要: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.
摘要翻译: 为了在集成电路制造期间进行图案化,形成第一掩模结构的第一图案,并且在第一掩模结构的暴露表面上形成缓冲层。 此外,在第一掩蔽结构的侧壁处的缓冲层之间的凹部中形成第二掩模结构的第二图案。 此外,第一掩模结构和掩模结构由各自含高含碳材料的旋涂形成。 这样的第一和第二掩模结构以比传统光刻法更高的间距对目标层进行图案化。
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公开(公告)号:US08349200B2
公开(公告)日:2013-01-08
申请号:US13217544
申请日:2011-08-25
申请人: Shi-Yong Yi , Myeong-Cheol Kim , Dong-Ki Yoon , Kyung-Yub Jeon , Ji-Hoon Cha
发明人: Shi-Yong Yi , Myeong-Cheol Kim , Dong-Ki Yoon , Kyung-Yub Jeon , Ji-Hoon Cha
CPC分类号: H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/312 , H01L21/32139
摘要: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.
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公开(公告)号:US20110312183A1
公开(公告)日:2011-12-22
申请号:US13217544
申请日:2011-08-25
申请人: Shi-Yong Yi , Myeong-Cheol Kim , Dong-Ki Yoon , Kyung-Yub Jeon , Ji-Hoon Cha
发明人: Shi-Yong Yi , Myeong-Cheol Kim , Dong-Ki Yoon , Kyung-Yub Jeon , Ji-Hoon Cha
IPC分类号: H01L21/306 , H01L21/31
CPC分类号: H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/312 , H01L21/32139
摘要: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.
摘要翻译: 为了在集成电路制造期间进行图案化,形成第一掩模结构的第一图案,并且在第一掩模结构的暴露表面上形成缓冲层。 此外,在第一掩蔽结构的侧壁处的缓冲层之间的凹部中形成第二掩模结构的第二图案。 此外,第一掩模结构和掩模结构由各自含高含碳材料的旋涂形成。 这样的第一和第二掩模结构以比传统光刻法更高的间距对目标层进行图案化。
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公开(公告)号:US20090176376A1
公开(公告)日:2009-07-09
申请号:US12217784
申请日:2008-07-09
申请人: Shi-Yong Yi , Myeong-Cheol Kim , Dong-Ki Yoon , Kyung-Yub Jeon , Ji-Hoon Cha
发明人: Shi-Yong Yi , Myeong-Cheol Kim , Dong-Ki Yoon , Kyung-Yub Jeon , Ji-Hoon Cha
IPC分类号: H01L21/308
CPC分类号: H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/312 , H01L21/32139
摘要: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.
摘要翻译: 为了在集成电路制造期间进行图案化,形成第一掩模结构的第一图案,并且在第一掩模结构的暴露表面上形成缓冲层。 此外,在第一掩蔽结构的侧壁处的缓冲层之间的凹部中形成第二掩模结构的第二图案。 此外,第一掩模结构和掩模结构由各自含高含碳材料的旋涂形成。 这样的第一和第二掩模结构以比传统光刻法更高的间距对目标层进行图案化。
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