公开(公告)号：US6118726A

公开(公告)日：2000-09-12

申请号：US17012

申请日：1998-02-02

申请人： L. Brian Ji ,  Toshiaki Kirihata

发明人： L. Brian Ji ,  Toshiaki Kirihata

IPC分类号： G11C11/407 ,  G11C8/10 ,  G11C11/401 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A shared row decoder and shared row decoding method are disclosed herein which provides separate timed selection signals to each of a first memory unit and a second memory unit. The shared row decoder includes an address input circuit responsive to the states of a plurality of address signals and which provides an enabling or disabling input. In addition, first and second selection circuits are provided which are responsive to enabled conditions of first and second block selection inputs, first and second timing signals, respectively and enabling input of the address input circuit to provide separate timed selection signals to the first and second memory units, respectively.

摘要翻译： 本文公开了共享行解码器和共享行解码方法，其向第一存储器单元和第二存储器单元中的每一个提供单独的定时选择信号。 共享行解码器包括响应于多个地址信号的状态并且提供启用或禁用输入的地址输入电路。 此外，提供了第一和第二选择电路，其分别响应于第一和第二块选择输入的使能条件，第一和第二定时信号，并使地址输入电路的输入能够向第一和第二选择信号提供单独的定时选择信号 内存单元。

公开(公告)号：US6115310A

公开(公告)日：2000-09-05

申请号：US225343

申请日：1999-01-05

申请人： Dmitry G. Netis ,  L. Brian Ji ,  Toshiaki Kirihata

发明人： Dmitry G. Netis ,  L. Brian Ji ,  Toshiaki Kirihata

IPC分类号： G11C8/08 ,  G11C8/14 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/02

CPC分类号： G11C8/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C8/14

摘要： A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.

摘要翻译： 本文公开了一种字线激活延迟监视器电路，其包括位于存储器的数据存储阵列内的采样字线，其中采样字线由存储器内具有基本相同结构或位置的电路​​选择或激活，该电路选择或 激活数据存储阵列的字线。 公开了一种电路，其通过激活位于第二子阵列组的数据存储阵列内的采样字线来确定存储器内的第一子阵列组的字线激活延迟。 还公开了相应的方法。

公开(公告)号：US6038634A

公开(公告)日：2000-03-14

申请号：US17017

申请日：1998-02-02

申请人： L. Brian Ji ,  Toshiaki Kirihata

发明人： L. Brian Ji ,  Toshiaki Kirihata

IPC分类号： G11C11/407 ,  G11C8/10 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G06F12/06

CPC分类号： G11C8/10

摘要： A system is disclosed herein for stabilizing the current dissipation, voltage drop, and heating effects related to accessing blocks within first and second storage units of a double memory unit. The system includes a row selection unit located between the first and second storage units, which accesses storage locations of the first and second storage units according to first and second selection signals conducted from the outer extremities of the double memory unit to selected row locations. The blocks at corresponding distances from the outer extremities are numbered differently such that the sum of lengths of signal travel of the first and second selection signals to the numbered blocks remains relatively constant regardless of the block number which is selected for access.

摘要翻译： 本文公开了一种用于稳定与双存储器单元的第一和第二存储单元内的块访问相关的电流耗散，电压降和加热效应的系统。 该系统包括位于第一和第二存储单元之间的行选择单元，其根据从双存储器单元的外端传输到所选行位置的第一和第二选择信号访问第一和第二存储单元的存储位置。 与外部相对应的距离的块以不同的方式编号，使得第一和第二选择信号到编号的块的信号行程的长度之和保持相对恒定，而不管选择用于访问的块号。

公开(公告)号：US06636978B1

公开(公告)日：2003-10-21

申请号：US09441798

申请日：1999-11-17

申请人： Toshiaki Kirihata ,  L. Brian Ji ,  John Ross

发明人： Toshiaki Kirihata ,  L. Brian Ji ,  John Ross

IPC分类号： H04L700

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0812

摘要： Digital latency shift communication problems from a driver chip to a receiver chip are overcome by scheduling a data output latency, a data input latency, a data output command, and/or a data output command, such that data outputted by the driver chip is received by the receiver chip at the correct time. A digital shift detection circuit detects the offset of the actual latencies from predetermined latencies. The offset of the latency is fed back to the scheduling circuit to override the predetermined latencies and/or command inputs that control the chip. The offset can be directly back-fed to the chip driver or chip receiver to compensate for digital shifts. Digital shift detection is achieved by measuring actual latencies with a manufacturing stand-alone tester, or with a built-in tester integral to the system. The digital shift detection predicts the conditions that create a digital shift by way of a mathematical model.

摘要翻译： 通过调度数据输出延迟，数据输入延迟，数据输出命令和/或数据输出命令来克服从驱动器芯片到接收器芯片的数字等待时间移位通信问题，使得接收由驱动器芯片输出的数据 由接收芯片在正确的时间。 数字移位检测电路检测实际延迟与预定延迟的偏移。 延迟的偏移被反馈到调度电路以覆盖控制芯片的预定延迟和/或命令输入。 偏移可以直接回馈给芯片驱动器或芯片接收器，以补偿数字移位。 数字移位检测通过使用制造独立测试仪测量实际延迟，或内置测试仪与系统集成来实现。 数字移位检测预测了通过数学模型创建数字移位的条件。

公开(公告)号：US06185135B2

公开(公告)日：2001-02-06

申请号：US09225340

申请日：1999-01-05

申请人： Dmitry G. Netis ,  L. Brian Ji ,  Toshiaki Kirihata

发明人： Dmitry G. Netis ,  L. Brian Ji ,  Toshiaki Kirihata

IPC分类号： G11C700

CPC分类号： G11C5/063

摘要： A wordline activation delay monitor circuit is disclosed wherein at least one sample wordline and a sample wordline redundancy are located within the same data-storing array region of a memory, and a sample wordline selector is coupled to activate the sample wordline or sample wordline redundancy based on the state of a nonvolatile input. The wordline selector circuit may include one or both of a row decoder circuit or a wordline driver circuit which have substantially the same structure and location as row decoder circuits and wordline driver circuits used to activate wordlines within the data-storing array region.

摘要翻译： 公开了一种字线激活延迟监视电路，其中至少一个采样字线和采样字线冗余位于存储器的相同数据存储阵列区域内，并且采样字线选择器被耦合以激活采样字线或采样字线冗余 处于非易失性输入状态。 字线选择器电路可以包括行解码器电路或字线驱动器电路中的一个或两个，其具有与用于激活数据存储阵列区域内的字线的行解码器电路和字线驱动器电路基本相同的结构和位置。