公开(公告)号：US09392145B2

公开(公告)日：2016-07-12

申请号：US14570817

申请日：2014-12-15

Applicant: LATTICE SEMICONDUCTOR CORPORATION

Inventor： Jiong Huang ,  Yuan Chen ,  Tieshan Liu ,  Lianghai Li ,  Bing Zhang ,  Jian Zhu

IPC: G06T5/00 ,  H04N5/06 ,  H04N17/00 ,  H04N5/21

CPC classification number: H04N5/06 ,  G06T5/003 ,  G06T2207/10016 ,  G06T2207/30168 ,  H04N5/21 ,  H04N17/00

Abstract: A mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams is described. In one embodiment, a method includes calculating stability optimization of an image of a media stream based on a plurality of pixels of two or more consecutive frames relating to a plurality of phases of the image, calculating sharpness optimization of the image, and selecting a best phase of the plurality of phases based on the stability and sharpness optimization of the image. The best phase may represent the image such that the image is displayed in a manner in accordance with human vision perceptions.

公开(公告)号：US09883082B2

公开(公告)日：2018-01-30

申请号：US15520349

申请日：2014-10-30

Applicant: Lattice Semiconductor Corporation

Inventor： Genlin Liu ,  Bing Zhang

IPC: H04N5/06 ,  H04N5/95

CPC classification number: H04N5/06 ,  H04N5/95

Abstract: A device that stabilizes video timing signals from an analog video signal is provided. In one embodiment, such a device includes a video PLL controller and a vertical synchronization (Vsync) signal generator. The device output a clock for digital video data, where the clock follows the Vsync signal from the analog video but within the jitter requirements for the clock.

公开(公告)号：US20170171004A1

公开(公告)日：2017-06-15

申请号：US15358748

申请日：2016-11-22

Applicant: Lattice Semiconductor Corporation

Inventor： Qiming Wu ,  Bing Zhang ,  Fei Song

IPC: H04L27/227 ,  H04L25/03

CPC classification number: H04L27/2275 ,  H04L25/0272 ,  H04L25/03273 ,  H04L25/4917 ,  H04Q2213/03

Abstract: Embodiments of the present disclosure relate to methods and device for receiving PAM data stream. In an embodiment, a method comprises receiving a signal stream modulated with pulse amplitude modulation (PAM) associated with a plurality of bit patterns; determining boundary voltages for the plurality of bit patterns; and calibrating, based on the boundary voltages, a threshold voltage for use in recognition of the plurality of bit patterns. In this way, bit patterns may be accurately recognized based on the calibrated threshold voltage.

公开(公告)号：US10044539B2

公开(公告)日：2018-08-07

申请号：US15358748

申请日：2016-11-22

Applicant: Lattice Semiconductor Corporation

Inventor： Qiming Wu ,  Bing Zhang ,  Fei Song

IPC: H04B3/46 ,  H04B17/00 ,  H04Q1/20 ,  H04L27/227 ,  H04L25/03

Abstract: Embodiments of the present disclosure relate to methods and device for receiving PAM data stream. In an embodiment, a method comprises receiving a signal stream modulated with pulse amplitude modulation (PAM) associated with a plurality of bit patterns; determining boundary voltages for the plurality of bit patterns; and calibrating, based on the boundary voltages, a threshold voltage for use in recognition of the plurality of bit patterns. In this way, bit patterns may be accurately recognized based on the calibrated threshold voltage.

公开(公告)号：US20170318198A1

公开(公告)日：2017-11-02

申请号：US15520349

申请日：2014-10-30

Applicant: Lattice Semiconductor Corporation

Inventor： Genlin Liu ,  Bing Zhang

IPC: H04N5/06 ,  H04N5/95

CPC classification number: H04N5/06 ,  H04N5/95

Abstract: A device that stabilizes video timing signals from an analog video signal is provided. In one embodiment, such a device includes a video PLL controller and a vertical synchronization (Vsync) signal generator. The device output a clock for digital video data, where the clock follows the Vsync signal from the analog video but within the jitter requirements for the clock.