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    Distributed FPGA solution for high-performance computing in the cloud
    1.
    发明授权
    Distributed FPGA solution for high-performance computing in the cloud 有权

    公开(公告)号：US10834023B2

    公开(公告)日：2020-11-10

    申请号：US16550857

    申请日：2019-08-26

    Applicant: LDA Technologies Ltd.

    Inventor： Sergey Sardaryan ,  Mariya Sukiasyan ,  Vahan Sardaryan

    IPC: H04L12/933 ,  H04L29/08 ,  H04L12/931 ,  G06F9/455

    Abstract: A data processing system, method and device. A device can include a plurality of data cards having host interface connectors initially configured to transmit signals according to a first communication protocol and data card connectors that communicate with external devices using a different communication protocol. The data cards are converted so that the host interface connectors also transmit signals using the second communication protocol. The plurality of data cards are interconnected so that signals can be routed through the data cards to provide desired data processing functions. A cross-point switch fabric allows the signals to be routed to the appropriate data card or cards. Multiple devices can be interconnected to provide a distributed data processing grid providing access to the data processing functions for external devices that do not communicate using the first communication protocol.

    SYSTEMS AND METHODS FOR MEASURING LATENCY IN A NETWORK DEVICE
    4.
    发明申请
    SYSTEMS AND METHODS FOR MEASURING LATENCY IN A NETWORK DEVICE 有权

    公开(公告)号：US20210176153A1

    公开(公告)日：2021-06-10

    申请号：US17021337

    申请日：2020-09-15

    Applicant: LDA Technologies Ltd.

    Inventor： Sergey Sardaryan ,  Mariya Sukiasyan ,  Vahan Sardaryan

    IPC: H04L12/26 ,  H04L25/02 ,  H04L27/233

    Abstract: Systems and methods are provided for measuring latency in a network device, which can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.

    Systems and methods for timestamping a data event
    5.
    发明授权
    Systems and methods for timestamping a data event 有权

    公开(公告)号：US10797984B1

    公开(公告)日：2020-10-06

    申请号：US16871439

    申请日：2020-05-11

    Applicant: LDA Technologies Ltd.

    Inventor： Sergey Sardaryan ,  Mariya Sukiasyan ,  Vahan Sardaryan

    IPC: H04L12/26 ,  G06F1/14 ,  H04J3/06 ,  G06F1/08 ,  H04L29/06

    Abstract: Systems and methods are provided for timestamping, which can include a signal generator, a detector, a sampler, a pulse detector, a timer, and a time-stamper. The signal generator can define a signal profile. The detector can i) detect a data event, and, upon detecting the data event, ii) instruct the signal generator to change from operating in a first mode of operation to operating in a second mode of operation. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits. The pulse detector can detect a change in the signal profile by detecting a change in value in the plurality of bits. The timer can time the change in the signal profile to provide at least one detection time measurement. The time-stamper can record in association with the data event a timestamp based on the at least one detection time measurement.

    SYSTEMS AND METHODS FOR TIMING A SIGNAL
    6.
    发明申请
    SYSTEMS AND METHODS FOR TIMING A SIGNAL 有权

    公开(公告)号：US20230006903A1

    公开(公告)日：2023-01-05

    申请号：US17783962

    申请日：2020-12-09

    Applicant: LDA Technologies Ltd.

    Inventor： Sergey Sardaryan ,  Mariya Sukiasyan ,  Vahan Sardaryan

    IPC: H04L43/0852 ,  H04L43/106 ,  H04L43/022 ,  H04L7/00

    Abstract: Systems and methods are provided for timing signals, measuring latency, and/or timestamping. Some of the systems described herein can measure latency in a network device, and can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.

    Systems and methods for measuring latency in a network device
    7.
    发明授权
    Systems and methods for measuring latency in a network device 有权

    公开(公告)号：US11178036B2

    公开(公告)日：2021-11-16

    申请号：US17021337

    申请日：2020-09-15

    Applicant: LDA Technologies Ltd.

    Inventor： Sergey Sardaryan ,  Mariya Sukiasyan ,  Vahan Sardaryan

    IPC: H04L12/26 ,  H04L27/233 ,  H04L25/02

    Abstract: Systems and methods are provided for measuring latency in a network device, which can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.

    Systems and methods for timing a signal
    9.
    发明授权
    Systems and methods for timing a signal 有权

    公开(公告)号：US12028232B2

    公开(公告)日：2024-07-02

    申请号：US17783962

    申请日：2020-12-09

    Applicant: LDA Technologies Ltd.

    Inventor： Sergey Sardaryan ,  Mariya Sukiasyan ,  Vahan Sardaryan

    IPC: H04L43/08 ,  H04L7/00 ,  H04L43/022 ,  H04L43/0852 ,  H04L43/106

    CPC classification number: H04L43/0852 ,  H04L7/0033 ,  H04L43/022 ,  H04L43/106

    Abstract: Systems and methods are provided for timing signals, measuring latency, and/or timestamping. Some of the systems described herein can measure latency in a network device, and can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.

    Systems and methods for timing a signal
    10.
    发明授权
    Systems and methods for timing a signal 有权

    公开(公告)号：US10680792B1

    公开(公告)日：2020-06-09

    申请号：US16710258

    申请日：2019-12-11

    Applicant: LDA Technologies Ltd.

    Inventor： Sergey Sardaryan ,  Mariya Sukiasyan ,  Vahan Sardaryan

    IPC: H04L7/033

    Abstract: Systems and methods are provided for timing signals. The systems and methods can include a signal-timing FPGA circuit. The signal-timing FPGA circuit includes a serializer, a pulse detector, at least one slower portion, a timer, and a signal generator. The serializer can convert data streams between serial transmission and parallel transmission. The serializer includes a serial input sampler for sampling signals received at the serializer, and a clock multiplier for changing signal frequencies. The at least one slower portion has a slower clock speed. The slower clock speed is slower than a clock speed of the clock multiplier. The timer is in communication with the serializer. The signal generator can generate and transmit a signal including a pulse portion and a non-pulse portion to the serializer via the at least one slower portion. The pulse portion differs in value from the non-pulse portion of the signal.

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