公开(公告)号：US09954014B2

公开(公告)日：2018-04-24

申请号：US15245944

申请日：2016-08-24

Applicant: LG DISPLAY CO., LTD.

Inventor： Soyoung Noh ,  Jinchae Jeon ,  Seungchan Choi ,  Junho Lee ,  Youngjang Lee ,  Sungbin Ryu ,  Kitae Kim ,  Bokyoung Cho ,  Jeanhan Yoon ,  Uijin Chung ,  Jihye Lee ,  Eunsung Kim ,  Hyunsoo Shin ,  Kyeongju Moon ,  Hyojin Kim ,  Wonkyung Kim ,  Jeihyun Lee ,  Soyeon Je

IPC: H01L27/12 ,  H01L27/32 ,  H01L49/02 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L27/1248 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/3258 ,  H01L27/3262 ,  H01L28/60 ,  H01L29/41733 ,  H01L29/78675 ,  H01L29/7869

Abstract: A thin film transistor substrate having two different types of thin film transistors on the same substrate, and a display using the same are discussed. The thin film transistor substrate can include a substrate, a first thin film transistor (TFT), a second TFT, a first storage capacitor electrode, an oxide layer, a nitride layer, a second storage capacitor electrode, a planar layer and a pixel electrode. The first TFT is disposed in a first area, the second TFT is disposed in a second area, and the first storage capacitor electrode is disposed in a third area on the substrate respectively. The oxide layer covers the first and second TFTs, and exposes the first storage capacitor electrode. The nitride layer is disposed on the oxide layer and covers the first storage capacitor electrode. The second storage capacitor electrode overlaps with the first storage capacitor electrode on the nitride layer. The planar layer covers the first and second TFTs, and the second storage capacitor electrode. The pixel electrode is disposed on the planar layer.

公开(公告)号：US10068530B2

公开(公告)日：2018-09-04

申请号：US15283588

申请日：2016-10-03

Applicant: LG Display Co., Ltd.

Inventor： Youngjang Lee ,  Jeanhan Yoon

IPC: G09G3/3266 ,  G11C19/18 ,  G11C19/28 ,  G09G3/3233 ,  G09G3/3275

Abstract: Provided are an organic light-emitting diode (OLED) display and method of driving the same. An OLED display includes: a display panel including a plurality of pixels, each pixel including an OLED, an emission timing of each pixel being controlled in response to an EM signal, a shift register configured to generate an anti-phase EM signal based on gate shift clocks, and an inverter configured to: invert a phase of the anti-phase EM signal based on emission shift clocks, and generate the EM signal, wherein a driving frequency of the shift register and a driving frequency of the inverter are lower in a low-speed driving mode than in a normal driving mode, and wherein in the low-speed driving mode, an amplitude of the emission shift clocks is less than an amplitude of the gate shift clocks.