公开(公告)号：US20160182042A1

公开(公告)日：2016-06-23

申请号：US14969280

申请日：2015-12-15

Applicant: LG Display Co., Ltd.

Inventor： DongSoo Kim ,  Hun Jeoung ,  SangHee Yu ,  SungHyun Cho ,  BoSun Lee ,  Sungwook Chang

IPC: H03K17/687 ,  G09G3/20 ,  G06F1/04

CPC classification number: H03K17/6871 ,  G06F1/04 ,  G09G3/2092 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0224 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G11C19/28

Abstract: A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node. The gate driver includes a plurality of stages, and each stage includes a pull-up transistor that outputs a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor that outputs a first source voltage input to a first source voltage terminal to the output terminal depending on a voltage of a pull-down node; and a first noise removing unit that supplies a gate-off voltage to the pull-up node to remove noise of the pull-up node in response to the clock signal input to the first clock terminal.

Abstract translation: 提供了一种栅极驱动器和包括栅极驱动器的显示装置，其可以通过稳定地维持上拉节点的放电电位来防止来自级的栅极 - 高电压的异常输出。 栅极驱动器包括多个级，并且每个级包括上拉晶体管，其根据上拉节点的电压将输入到第一时钟端子的时钟信号输出到输出端子; 下拉晶体管，其根据下拉节点的电压将输入到第一源极电压端子的第一源极电压输出到输出端子; 以及第一噪声去除单元，其向所述上拉节点提供栅极截止电压，以响应于输入到所述第一时钟端子的时钟信号来去除所述上拉节点的噪声。

公开(公告)号：US09774325B2

公开(公告)日：2017-09-26

申请号：US14969280

申请日：2015-12-15

Applicant: LG Display Co., Ltd.

Inventor： DongSoo Kim ,  Hun Jeoung ,  SangHee Yu ,  SungHyun Cho ,  BoSun Lee ,  Sungwook Chang

IPC: G09G3/36 ,  H03K17/687 ,  G09G3/3225 ,  G09G3/3266 ,  G11C19/28 ,  G06F1/04 ,  G09G3/20

CPC classification number: H03K17/6871 ,  G06F1/04 ,  G09G3/2092 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0224 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G11C19/28

Abstract: A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node. The gate driver includes a plurality of stages, and each stage includes a pull-up transistor that outputs a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor that outputs a first source voltage input to a first source voltage terminal to the output terminal depending on a voltage of a pull-down node; and a first noise removing unit that supplies a gate-off voltage to the pull-up node to remove noise of the pull-up node in response to the clock signal input to the first clock terminal.