公开(公告)号：US10025413B2

公开(公告)日：2018-07-17

申请号：US14841534

申请日：2015-08-31

Applicant: LG Display Co., Ltd.

Inventor： DongSoo Kim ,  SangHee Yu ,  SangWoon Kim

IPC: G06F3/041 ,  G06F21/88 ,  H01L27/12 ,  H01L21/312 ,  H01L29/786 ,  H01L29/24 ,  G06F3/044

Abstract: A touch recognition enabled display panel includes a plurality of common electrode blocks serving as touch-sensing regions and/or touch-driving regions. Conductive lines connected to the common electrode blocks are placed under the common electrode blocks and the pixel electrodes of the pixels, and they are routed across the active area, directly toward an inactive area where drive-integrated circuits are located. The conductive lines are positioned under one or more planarization layers, and are connected to the corresponding common electrode blocks via one or more contact holes.

公开(公告)号：US20160182042A1

公开(公告)日：2016-06-23

申请号：US14969280

申请日：2015-12-15

Applicant: LG Display Co., Ltd.

Inventor： DongSoo Kim ,  Hun Jeoung ,  SangHee Yu ,  SungHyun Cho ,  BoSun Lee ,  Sungwook Chang

IPC: H03K17/687 ,  G09G3/20 ,  G06F1/04

CPC classification number: H03K17/6871 ,  G06F1/04 ,  G09G3/2092 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0224 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G11C19/28

Abstract: A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node. The gate driver includes a plurality of stages, and each stage includes a pull-up transistor that outputs a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor that outputs a first source voltage input to a first source voltage terminal to the output terminal depending on a voltage of a pull-down node; and a first noise removing unit that supplies a gate-off voltage to the pull-up node to remove noise of the pull-up node in response to the clock signal input to the first clock terminal.

Abstract translation: 提供了一种栅极驱动器和包括栅极驱动器的显示装置，其可以通过稳定地维持上拉节点的放电电位来防止来自级的栅极 - 高电压的异常输出。 栅极驱动器包括多个级，并且每个级包括上拉晶体管，其根据上拉节点的电压将输入到第一时钟端子的时钟信号输出到输出端子; 下拉晶体管，其根据下拉节点的电压将输入到第一源极电压端子的第一源极电压输出到输出端子; 以及第一噪声去除单元，其向所述上拉节点提供栅极截止电压，以响应于输入到所述第一时钟端子的时钟信号来去除所述上拉节点的噪声。

公开(公告)号：US20170060317A1

公开(公告)日：2017-03-02

申请号：US14841534

申请日：2015-08-31

Applicant: LG Display Co., Ltd.

Inventor： DongSoo Kim ,  SangHee Yu ,  SangWoon Kim

IPC: G06F3/041 ,  G06F3/044 ,  H01L29/24 ,  H01L27/12 ,  H01L29/786

CPC classification number: G06F3/0416 ,  G06F3/0412 ,  G06F3/044 ,  G06F2203/04103 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869

Abstract: A touch recognition enabled display panel includes a plurality of common electrode blocks serving as touch-sensing regions and/or touch-driving regions. Conductive lines connected to the common electrode blocks are placed under the common electrode blocks and the pixel electrodes of the pixels, and they are routed across the active area, directly toward an inactive area where drive-integrated circuits are located. The conductive lines are positioned under one or more planarization layers, and are connected to the corresponding common electrode blocks via one or more contact holes.

Abstract translation: 触摸识别启用显示面板包括用作触摸感测区域和/或触摸驱动区域的多个公共电极块。 连接到公共电极块的导电线被放置在公共电极块和像素的像素电极之下，并且它们被直接穿过有源区域路由到驱动集成电路所在的无效区域。 导线位于一个或多个平坦化层之下，并且经由一个或多个接触孔连接到相应的公共电极块。

公开(公告)号：US08921850B2

公开(公告)日：2014-12-30

申请号：US13728732

申请日：2012-12-27

Applicant: LG Display Co., Ltd.

Inventor： SangHee Yu

IPC: H01L29/786 ,  H01L27/15 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L27/153 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606

Abstract: A thin film transistor (TFT), a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the same are provided. An oxide thin film transistor (TFT) includes: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer above the gate electrode; an etch stop layer pattern formed on the active layer; a source alignment element and a drain alignment element formed on the etch stop layer pattern and spaced apart from one another; and a source electrode in contact with the source alignment element and the active layer and a drain electrode in contact with the drain alignment element and the active layer.

Abstract translation: 提供薄膜晶体管（TFT），TFT制造方法，具有TFT的显示装置用阵列基板及其制造方法。 氧化物薄膜晶体管（TFT）包括：形成在基板上的栅电极; 形成在所述栅电极上的栅极绝缘层; 形成在栅电极上方的栅极绝缘层上的有源层; 形成在有源层上的蚀刻停止层图案; 形成在蚀刻停止层图案上并彼此分开的源极对准元件和漏极对准元件; 以及与源极对准元件和有源层接触的源极和与漏极对准元件和有源层接触的漏电极。

公开(公告)号：US09766506B2

公开(公告)日：2017-09-19

申请号：US14714799

申请日：2015-05-18

Applicant: LG DISPLAY CO., LTD.

Inventor： Heonkwang Park ,  SangHee Yu ,  SungHyun Cho ,  SangWoon Kim ,  TaeSang Kim

IPC: G02F1/1339 ,  G02F1/1335 ,  G02F1/1333

CPC classification number: G02F1/13394 ,  G02F1/133512 ,  G02F2001/133357

Abstract: A liquid crystal display panel includes features to prevent damage to the liquid crystal alignment layer when a color filter substrate and a thin-film transistor array substrate are moved relative to each other. The liquid crystal display panel may include a column spacer on the color filter substrate under the black matrix and a bump pattern on the array substrate where the column spacer and the bump pattern are in contact with each other. The array substrate may otherwise include a planarization layer with a step portion and a protective layer on the planarization layer where the protective layer is in contact with the column spacer.

公开(公告)号：US10176774B2

公开(公告)日：2019-01-08

申请号：US15220911

申请日：2016-07-27

Applicant: LG DISPLAY CO., LTD.

Inventor： Byoungwoo Kim ,  SangHee Yu

IPC: G09G3/36

Abstract: An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.

公开(公告)号：US10114258B2

公开(公告)日：2018-10-30

申请号：US15167369

申请日：2016-05-27

Applicant: LG DISPLAY CO., LTD.

Inventor： SangWoon Kim ,  SangHee Yu ,  SungHyun Cho ,  SangGul Lee

IPC: G02F1/1345 ,  G02F1/1339 ,  G02F1/133 ,  H01L27/12 ,  H01L51/52 ,  H01L27/32 ,  G02F1/1343

Abstract: A display device according to an embodiment includes a lower substrate in which a display area and a non-display area are divided and an upper substrate which corresponds to the lower substrate and includes a black matrix BM. Further, the display device can include a bezel which is located on the non-display area and includes a GIP driver, a plurality of signal transmission lines, a connection line connecting the GIP driver and the plurality of signal transmission lines, and a seal area equipped with a sealant, in a direction being apart from one side of the display area, a plurality of bridge patterns which is located on the non-display area and electrically connects the GIP driver and the connection line, and the connection line and the plurality of signal transmission lines, respectively, and a plurality of shield patterns enclosing the plurality of bridge patterns. Also, the display device can include a plurality of shield patterns which minimize an area in which the sealant and the plurality of bridge patterns are in directly contact with each other.

公开(公告)号：US09774325B2

公开(公告)日：2017-09-26

申请号：US14969280

申请日：2015-12-15

Applicant: LG Display Co., Ltd.

Inventor： DongSoo Kim ,  Hun Jeoung ,  SangHee Yu ,  SungHyun Cho ,  BoSun Lee ,  Sungwook Chang

IPC: G09G3/36 ,  H03K17/687 ,  G09G3/3225 ,  G09G3/3266 ,  G11C19/28 ,  G06F1/04 ,  G09G3/20

CPC classification number: H03K17/6871 ,  G06F1/04 ,  G09G3/2092 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0224 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G11C19/28

Abstract: A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node. The gate driver includes a plurality of stages, and each stage includes a pull-up transistor that outputs a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor that outputs a first source voltage input to a first source voltage terminal to the output terminal depending on a voltage of a pull-down node; and a first noise removing unit that supplies a gate-off voltage to the pull-up node to remove noise of the pull-up node in response to the clock signal input to the first clock terminal.