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公开(公告)号:US11107388B2
公开(公告)日:2021-08-31
申请号:US15498584
申请日:2017-04-27
Applicant: LG Display Co., Ltd.
Inventor: SungHyun Cho , ChungSik Kong , Byoungwoo Kim , Sungwook Chang , DongSoo Kim
Abstract: A gate driving circuit and a display device are disclosed. The gate driving circuit includes a shift register including a plurality of stages. Among the stages, an Nth stage includes a first transistor charging a Q node and a junction stress control circuit. A pull-up transistor using the Q node as a gate input controls an output signal of a stage output terminal. The junction stress control circuit includes a first, second, and third control transistors. The first control transistor, the second control transistor, the third control transistor, and the first transistor are connected to each other through a common node. The second control transistor adjusts junction stresses for the first control transistor and the first transistor by controlling a voltage of the common node. When the second control transistor is turned off, the third control transistor discharges the voltage of the common node.
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公开(公告)号:US09766506B2
公开(公告)日:2017-09-19
申请号:US14714799
申请日:2015-05-18
Applicant: LG DISPLAY CO., LTD.
Inventor: Heonkwang Park , SangHee Yu , SungHyun Cho , SangWoon Kim , TaeSang Kim
IPC: G02F1/1339 , G02F1/1335 , G02F1/1333
CPC classification number: G02F1/13394 , G02F1/133512 , G02F2001/133357
Abstract: A liquid crystal display panel includes features to prevent damage to the liquid crystal alignment layer when a color filter substrate and a thin-film transistor array substrate are moved relative to each other. The liquid crystal display panel may include a column spacer on the color filter substrate under the black matrix and a bump pattern on the array substrate where the column spacer and the bump pattern are in contact with each other. The array substrate may otherwise include a planarization layer with a step portion and a protective layer on the planarization layer where the protective layer is in contact with the column spacer.
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公开(公告)号:US20160182042A1
公开(公告)日:2016-06-23
申请号:US14969280
申请日:2015-12-15
Applicant: LG Display Co., Ltd.
Inventor: DongSoo Kim , Hun Jeoung , SangHee Yu , SungHyun Cho , BoSun Lee , Sungwook Chang
IPC: H03K17/687 , G09G3/20 , G06F1/04
CPC classification number: H03K17/6871 , G06F1/04 , G09G3/2092 , G09G3/3225 , G09G3/3266 , G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2300/0809 , G09G2310/0224 , G09G2310/0286 , G09G2310/08 , G09G2320/0214 , G11C19/28
Abstract: A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node. The gate driver includes a plurality of stages, and each stage includes a pull-up transistor that outputs a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor that outputs a first source voltage input to a first source voltage terminal to the output terminal depending on a voltage of a pull-down node; and a first noise removing unit that supplies a gate-off voltage to the pull-up node to remove noise of the pull-up node in response to the clock signal input to the first clock terminal.
Abstract translation: 提供了一种栅极驱动器和包括栅极驱动器的显示装置,其可以通过稳定地维持上拉节点的放电电位来防止来自级的栅极 - 高电压的异常输出。 栅极驱动器包括多个级,并且每个级包括上拉晶体管,其根据上拉节点的电压将输入到第一时钟端子的时钟信号输出到输出端子; 下拉晶体管,其根据下拉节点的电压将输入到第一源极电压端子的第一源极电压输出到输出端子; 以及第一噪声去除单元,其向所述上拉节点提供栅极截止电压,以响应于输入到所述第一时钟端子的时钟信号来去除所述上拉节点的噪声。
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公开(公告)号:US10725342B2
公开(公告)日:2020-07-28
申请号:US15238948
申请日:2016-08-17
Applicant: LG Display Co., Ltd.
Inventor: SungHyun Cho , SangWoon Kim
IPC: G02F1/1339
Abstract: A liquid crystal display device is provided. The liquid crystal display device includes a first substrate having elements configured to drive pixels; a second substrate having color filters corresponding to the pixels; and a sealant configured to bond the first substrate and the second substrate to each other. The first substrate includes a first protruding structure located in an area in contact with the sealant and the second substrate includes a second protruding structure located in an area in contact with the sealant.
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公开(公告)号:US10114258B2
公开(公告)日:2018-10-30
申请号:US15167369
申请日:2016-05-27
Applicant: LG DISPLAY CO., LTD.
Inventor: SangWoon Kim , SangHee Yu , SungHyun Cho , SangGul Lee
IPC: G02F1/1345 , G02F1/1339 , G02F1/133 , H01L27/12 , H01L51/52 , H01L27/32 , G02F1/1343
Abstract: A display device according to an embodiment includes a lower substrate in which a display area and a non-display area are divided and an upper substrate which corresponds to the lower substrate and includes a black matrix BM. Further, the display device can include a bezel which is located on the non-display area and includes a GIP driver, a plurality of signal transmission lines, a connection line connecting the GIP driver and the plurality of signal transmission lines, and a seal area equipped with a sealant, in a direction being apart from one side of the display area, a plurality of bridge patterns which is located on the non-display area and electrically connects the GIP driver and the connection line, and the connection line and the plurality of signal transmission lines, respectively, and a plurality of shield patterns enclosing the plurality of bridge patterns. Also, the display device can include a plurality of shield patterns which minimize an area in which the sealant and the plurality of bridge patterns are in directly contact with each other.
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公开(公告)号:US09774325B2
公开(公告)日:2017-09-26
申请号:US14969280
申请日:2015-12-15
Applicant: LG Display Co., Ltd.
Inventor: DongSoo Kim , Hun Jeoung , SangHee Yu , SungHyun Cho , BoSun Lee , Sungwook Chang
IPC: G09G3/36 , H03K17/687 , G09G3/3225 , G09G3/3266 , G11C19/28 , G06F1/04 , G09G3/20
CPC classification number: H03K17/6871 , G06F1/04 , G09G3/2092 , G09G3/3225 , G09G3/3266 , G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2300/0809 , G09G2310/0224 , G09G2310/0286 , G09G2310/08 , G09G2320/0214 , G11C19/28
Abstract: A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node. The gate driver includes a plurality of stages, and each stage includes a pull-up transistor that outputs a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor that outputs a first source voltage input to a first source voltage terminal to the output terminal depending on a voltage of a pull-down node; and a first noise removing unit that supplies a gate-off voltage to the pull-up node to remove noise of the pull-up node in response to the clock signal input to the first clock terminal.
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