公开(公告)号：US20040266078A1

公开(公告)日：2004-12-30

申请号：US10661486

申请日：2003-09-15

Applicant: LG.Philips LCD Co., Ltd.

Inventor： Sang Hyun Kim

IPC: H01L021/00 ,  C30B001/00 ,  H01L021/477 ,  H01L021/84

CPC classification number: H01L21/0268 ,  H01L21/02532 ,  H01L21/02691 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675

Abstract: A crystallization method of an amorphous semiconductor layer includes providing an amorphous semiconductor layer having a first thickness, crystallizing the amorphous semiconductor layer in a first direction, partially reducing the crystallized semiconductor layer to a second thickness less than the first thickness and crystallizing the etched semiconductor layer in a second direction.

Abstract translation: 非晶半导体层的结晶方法包括提供具有第一厚度的非晶半导体层，在第一方向上使非晶半导体层结晶，将结晶化半导体层部分地还原成小于第一厚度的第二厚度并使蚀刻的半导体层结晶 在第二个方向。

公开(公告)号：US20040263742A1

公开(公告)日：2004-12-30

申请号：US10863235

申请日：2004-06-09

Applicant: LG.PHILIPS LCD CO., LTD.

Inventor： Sang Hyun Kim

IPC: G02F001/1343

CPC classification number: G02F1/136227

Abstract: A method of fabricating a liquid crystal display device includes forming a data bus line on a substrate, forming a preliminary interlayer insulating layer having a first thickness on the substrate including the data bus line, forming an interlayer insulating layer by etching the preliminary interlayer insulating layer to a second thickness less than the first thickness, the interlayer insulating layer having a planarized surface, sequentially forming a semiconductor layer, a gate insulating layer, and a gate electrode on the interlayer insulating layer, forming a passivation layer on the substrate, forming a plurality of contact holes exposing portions of the data bus line and the semiconductor layer by etching portions of the passivation layer, and forming a pixel electrode on the passivation layer.

Abstract translation: 一种液晶显示装置的制造方法，其特征在于，在基板上形成数据总线，在包括所述数据总线的基板上形成具有第一厚度的预备层间绝缘层，通过蚀刻所述初始层间绝缘层 所述层间绝缘层具有平坦化表面，在所述层间绝缘层上依次形成半导体层，栅极绝缘层和栅电极，在所述基板上形成钝化层，形成所述第一厚度， 多个接触孔通过蚀刻钝化层的部分而暴露数据总线和半导体层的部分，以及在钝化层上形成像素电极。