公开(公告)号：US20150243363A1

公开(公告)日：2015-08-27

申请号：US14195058

申请日：2014-03-03

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Zhengang Chen ,  AbdelHakim S. Alhussien ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/26

CPC classification number: G11C11/5642 ,  G06F11/1048 ,  G06F11/1072 ,  G11C29/52

Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values.

Abstract translation: 公开了一种具有电路和与非易失性存储器的接口的装置。 电路被配置为（i）执行对存储在非易失性存储器中的数据的软判决解码的一个或多个尝试，其中软判决解码使用存储在表中的多个对数似然比值，（ii）生成一个 或更多调整的对数似然比值，通过将响应于使用对数似然比值对数据进行解码的一个或多个对数似然比值来增加常数值，以及（iii）使用调整后的记录重新解码数据 似然比值。

公开(公告)号：US20150194219A1

公开(公告)日：2015-07-09

申请号：US14155687

申请日：2014-01-15

Applicant: LSI Corporation

Inventor： Meysam Asadi ,  Zhengang Chen ,  Erich F. Haratsch

IPC: G11C16/34 ,  G01R27/26 ,  G06F17/17

CPC classification number: G01R27/2605 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3422 ,  G11C16/3427

Abstract: A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to the memory cells. The voltages are determined in each of a plurality of cases related to inter-cell interference. Step (B) generates a system of equations of a capacitance coupling model in response to the voltages from all of the cases. Step (C) generates one or more parameters in response to the system of equations. The parameters include one or more couplings between a perturbed memory cell and a plurality of neighboring memory cells adjacent to the perturbed memory cell.

Abstract translation: 公开了一种用于电容耦合参数估计的方法。 响应于对存储器单元的多次写入，该方法的步骤（A）确定非易失性存储器的多个存储单元中的多个电压。 在与小区间干扰有关的多种情况中的每一种情况下确定电压。 步骤（B）响应于来自所有情况的电压产生电容耦合模型的方程组。 步骤（C）响应于方程式生成一个或多个参数。 这些参数包括扰动的存储器单元和与扰动的存储单元相邻的多个相邻存储器单元之间的一个或多个耦合。

公开(公告)号：US20150149856A1

公开(公告)日：2015-05-28

申请号：US14136380

申请日：2013-12-20

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Zhengang Chen ,  Erich F. Haratsch

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1068 ,  G11C11/5642

Abstract: An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.

Abstract translation: 公开了一种具有一个或多个查找表和解码器的装置。 查找表被配置为存储多组对数似然比值。 解码器被配置为（i）接收从存储器读取的码字，（ii）从查找表接收集合中的初始一个集合，以及（iii）基于该值对码字进行解码来生成读取数据。

公开(公告)号：US09021331B2

公开(公告)日：2015-04-28

申请号：US13893832

申请日：2013-05-14

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Zhengang Chen ,  Erich F. Haratsch

IPC: G06F11/10 ,  H03M13/11 ,  H03M7/42 ,  H03M13/29 ,  H03M13/45 ,  H03M13/00

CPC classification number: G06F11/1068 ,  H03M7/42 ,  H03M13/00 ,  H03M13/1111 ,  H03M13/1125 ,  H03M13/2927 ,  H03M13/45

Abstract: A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision information provided by the lookup table and assigned to the appropriate cells of the flash memory device.

Abstract translation: 一种用于产生软判决纠错码信息的方法和装置。 该方法包括生成或创建表征闪存设备的查找表（LUT），诸如对数似然比（LLR）查找表。 该方法还包括将查找表加载到SSD控制器中。 该方法还包括访问查找表以向闪存设备的单元分配LLR或其他特征值。 该方法还包括使用由查找表提供并分配给闪存设备的适当单元的软判决信息对闪存设备中的数据进行解码。

公开(公告)号：US20150113354A1

公开(公告)日：2015-04-23

申请号：US14064524

申请日：2013-10-28

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Zhengang Chen ,  Erich F. Haratsch

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0411

Abstract: A flash memory controller having soft-decoding error correcting code (ECC) logic generates log likelihood ratio or similar ECC decoder soft input information from decision patterns obtained from reading data from the same portion of flash memory two or more times. Each decision pattern corresponds to a voltage region bordering one of the reference voltages. Each decision pattern represents a combination of flash memory bit value decisions for a cell voltage within the voltage region corresponding to the decision pattern when a corresponding combination of the reference voltages are used to read the cell. Numerical values are then computed in response to combinations of the flash memory bit value decisions represented by the decision patterns. The numerical values are provided to the soft-decoding ECC logic to serve as soft input information.

Abstract translation: 具有软解码错误校正码（ECC）逻辑的闪速存储器控制器从从闪速存储器的相同部分读取数据两次或更多次的判定模式生成对数似然比或类似的ECC解码器软输入信息。 每个判定模式对应于与参考电压之一相邻的电压区域。 每个判定模式表示当使用参考电压的相应组合来读取单元时，与对应于判定模式的电压区域内的单元电压的闪存位值决定的组合。 然后响应于由决策模式表示的闪存位值决定的组合来计算数值。 将数值提供给软解码ECC逻辑以用作软输入信息。

公开(公告)号：US20150082121A1

公开(公告)日：2015-03-19

申请号：US14041110

申请日：2013-09-30

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Zhengang Chen ,  Yu Cai ,  Erich F. Haratsch

IPC: G06F12/02 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F3/06 ,  G06F13/16 ,  G11C11/5635 ,  G11C16/00 ,  G11C16/14 ,  G11C16/349

Abstract: An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters.

Abstract translation: 一种装置包括非易失性存储器和控制器。 控制器可以被配置为跟踪非易失性存储器的一个或多个信道参数。 控制器还可以被配置为基于一个或多个信道参数中的至少一个从查找表中选择一个或多个擦除状态分布的参数来估计非易失性存储器的擦除状态电压分布。

公开(公告)号：US20140164881A1

公开(公告)日：2014-06-12

申请号：US13804671

申请日：2013-03-14

Applicant: LSI CORPORATION

Inventor： Zhengang Chen ,  Earl T. Cohen ,  Jeremy Werner ,  Erich F. Haratsch

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1666 ,  G06F11/20 ,  G11C16/00 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: An apparatus includes a non-volatile memory and a controller. The controller is operatively coupled to the non-volatile memory and configured to perform read and write operations on the non-volatile memory using codewords as a unit of read access. The controller includes an error correction engine configured to perform an error correction on codewords read from the non-volatile memory, and, if the error correction fails, to perform one or more retry procedures. The controller is further configured to perform one or more background procedures as a result of the error correction or one or more of the retry procedures not being successful and send an error message as a result of all of the retry procedures not being successful. The one or more background procedures are directed to determining a cause of the error correction failure.

Abstract translation: 一种装置包括非易失性存储器和控制器。 控制器可操作地耦合到非易失性存储器并且被配置为使用作为读取访问的单元的码字来对非易失性存储器执行读取和写入操作。 所述控制器包括错误校正引擎，其被配置为对从所述非易失性存储器读取的码字执行错误校正，并且如果所述错误校正失败，则执行一个或多个重试过程。 控制器还被配置为作为纠错的结果执行一个或多个后台过程，或者一个或多个重试过程不成功，并且由于所有重试过程不成功而发送错误消息。 一个或多个背景程序涉及确定纠错失败的原因。

公开(公告)号：US20150149871A1

公开(公告)日：2015-05-28

申请号：US14093110

申请日：2013-11-29

Applicant: LSI Corporation

Inventor： Zhengang Chen ,  Yunxiang Wu ,  AbdelHakim S. Alhussien ,  Erich F. Haratsch

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1105

Abstract: An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.

Abstract translation: 一种用于读取闪速存储器的装置，包括：读取控制器，用于读取闪速存储器以产生读取模式;可能性生成器，用于将读取模式映射到似然值;可解码器，用于解码似然值;数据状态存储器， 检索解码失败的似然值，以及选择性衰减控制器，可操作以从解码失败的似然值中选择至少一个衰减候选，以抑制至少一个阻尼候选的似然值以产生阻尼似然值， 并向解码器提供衰减似然值以进行解码。

公开(公告)号：US09036413B2

公开(公告)日：2015-05-19

申请号：US14059229

申请日：2013-10-21

Applicant: LSI Corporation

Inventor： Yunxiang Wu ,  Abdel-Hakim Alhussien ,  Zhengang Chen ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028

Abstract: Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations.

Abstract translation: 通过使用两个或更多个不同的候选参考电压从闪速存储器的一部分读取数据两次或更多次来确定快闪存储器单元电压分布的交点，并确定相应的判定模式。 使用从闪存读取的数据中的判定模式的发生频率来概念地构造直方图。 直方图用于估计交叉点。 采用决策模式可以通过最少的读取操作来确定多个交叉点电压。

公开(公告)号：US20150127883A1

公开(公告)日：2015-05-07

申请号：US14087520

申请日：2013-11-22

Applicant: LSI Corporation

Inventor： Zhengang Chen ,  Erich F. Haratsch ,  Sundararajan Sankaranarayanan

IPC: G06F12/02

CPC classification number: G11C16/28 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1402 ,  G11C7/14 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028

Abstract: Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made during normal read operations.

Abstract translation: 由离线跟踪过程确定的通道信息和通道条件用于确定是否可以完全避免对读取参考电压的调整，而不会对性能造成不利影响，或者替代地，确定读取参考电压的精度 应作出调整。 如果基于通道条件确定可以完全避免读取参考电压调整，则通过降低在正常读取操作期间需要进行读取参考电压调整的可能性来改善读取性能。 如果基于通道条件确定需要以特定精度进行读取参考电压调整，则以该精度调整读取的参考电压。 后一种方法的优点在于，确定可以进行调整的精度相对较低导致在正常读取操作期间必须进行较少的调整。