公开(公告)号：US08898549B2

公开(公告)日：2014-11-25

申请号：US13765034

申请日：2013-02-12

Applicant: LSI Corporation

Inventor： Alexander Hubris ,  Hao Zhong

IPC: H03M13/00 ,  G06F11/10 ,  H04L1/00 ,  H03M13/35

CPC classification number: G06F11/10 ,  G06F11/1048 ,  H03M13/35 ,  H03M13/353 ,  H04L1/0009

Abstract: A method for implementing adaptive error correction in a memory, comprising the steps of (A) decoding a page of data read from a memory, (B) selecting one of a plurality of histograms based on a measured code word error rate of the decoded page and (C) applying an error correction code rate based on the selected histogram. The error correction code rate allows the memory to use a minimum number of error correction bits to provide reliable operation of the memory.

Abstract translation: 一种用于在存储器中实现自适应纠错的方法，包括以下步骤：（A）解码从存储器读取的数据页面，（B）基于所解码页面的测量码字错误率来选择多个直方图中的一个 和（C）基于所选择的直方图应用纠错码率。 纠错码率允许存储器使用最小数量的纠错位来提供存储器的可靠操作。

公开(公告)号：US20140229799A1

公开(公告)日：2014-08-14

申请号：US13765034

申请日：2013-02-12

Applicant: LSI CORPORATION

Inventor： Alexander Hubris ,  Hao Zhong

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1048 ,  H03M13/35 ,  H03M13/353 ,  H04L1/0009

Abstract: A method for implementing adaptive error correction in a memory, comprising the steps of (A) decoding a page of data read from a memory, (B) selecting one of a plurality of histograms based on a measured code word error rate of the decoded page and (C) applying an error correction code rate based on the selected histogram. The error correction code rate allows the memory to use a minimum number of error correction bits to provide reliable operation of the memory.

Abstract translation: 一种用于在存储器中实现自适应纠错的方法，包括以下步骤：（A）解码从存储器读取的数据页面，（B）基于所解码页面的测量码字错误率来选择多个直方图中的一个 和（C）基于所选择的直方图应用纠错码率。 纠错码率允许存储器使用最小数量的纠错位来提供存储器的可靠操作。

公开(公告)号：US09037945B2

公开(公告)日：2015-05-19

申请号：US13852852

申请日：2013-03-28

Applicant: LSI Corporation

Inventor： YingQuan Wu ,  Ivana Djurdjevic ,  Alexander Hubris

IPC: H03M13/00 ,  H03M13/11

CPC classification number: H03M13/116 ,  H03M13/611 ,  H03M13/616

Abstract: A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H′; and constructing the generator matrix G based on the rearranged parity check matrix H′.

Abstract translation: 公开了一种用于构建发电机矩阵的方法和系统。 该方法包括：接收奇偶校验矩阵H，其中奇偶校验矩阵H包括多个循环子矩阵; 通过列和行排列重排奇偶校验矩阵H以获得重新排列的奇偶校验矩阵H'; 以及基于重新排列的奇偶校验矩阵H'构建生成矩阵G.

公开(公告)号：US20150135031A1

公开(公告)日：2015-05-14

申请号：US14092215

申请日：2013-11-27

Applicant: LSI Corporation

Inventor： Earl T. Cohen ,  Yunxiang Wu ,  Alexander Hubris ,  Christopher Brewer

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

Abstract: An apparatus includes one or more error-correction decoders, a buffer, at least one direct memory access (DMA) engine, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one DMA engine may couple the buffer and the one or more error-correction decoders. The at least one processor may be enabled to send messages to the at least one DMA engine. The messages may be configured to deliver DMA control information and corresponding datapath control information. Data may be read from the buffer based upon the DMA control information and delivered to the one or more error-correction decoders along with the corresponding datapath control information. The one or more error-correction decoders may be enabled to decode the data read from the buffer according to the corresponding datapath control information.

Abstract translation: 一种装置包括一个或多个纠错解码器，缓冲器，至少一个直接存储器访问（DMA）引擎和至少一个处理器。 缓冲器可以被配置为存储要由一个或多个纠错解码器解码的数据。 至少一个DMA引擎可以耦合缓冲器和一个或多个纠错解码器。 可以使至少一个处理器能够向至少一个DMA引擎发送消息。 消息可以被配置为递送DMA控制信息和相应的数据路径控制信息。 可以基于DMA控制信息从缓冲器读取数据，并将其与相应的数据路径控制信息一起递送到一个或多个纠错解码器。 可以使一个或多个纠错解码器根据相应的数据路径控制信息解码从缓冲器读取的数据。

公开(公告)号：US20150026536A1

公开(公告)日：2015-01-22

申请号：US13958162

申请日：2013-08-02

Applicant: LSI Corporation

Inventor： Alexander Hubris ,  Zhengang Chen ,  AbdelHakim S. Alhussien ,  YingQuan Wu

IPC: G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/10 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1142 ,  H03M13/116 ,  H03M13/1171 ,  H03M13/6561 ,  H03M13/658

Abstract: A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.

Abstract translation: 低密度奇偶校验解码器包括可变节点处理器，其可操作以生成可变节点以校验节点消息，并且基于对可变节点消息的校验节点来计算感知值;校验节点处理器，可操作以将校验节点生成到可变节点消息向量;以及 基于变量节点来计算校验和以检查节点消息;以及收敛检测器和位图生成器，其可操作用于感知值的收敛并生成至少一个位图，其识别连接到具有不满足奇偶校验检查的节点的变量节点 。

公开(公告)号：US20150106666A1

公开(公告)日：2015-04-16

申请号：US14052732

申请日：2013-10-12

Applicant: LSI Corporation

Inventor： Alexander Hubris ,  Vidyuth Srivatsaa ,  Bing Ji

IPC: G06F11/07

CPC classification number: H04L1/005 ,  G06F11/10 ,  H04L1/0057 ,  H04L1/203

Abstract: An apparatus for calculating a speculative bit error rate includes a data decoder operable to iteratively decode received data to yield decoded data, and a speculative bit error calculator operable to calculate a bit error rate based on the decoded data and the received data while the data decoder is decoding the received data. The bit error rate is updated with each decoding iteration in the data decoder.

Abstract translation: 一种用于计算推测误比特率的装置，包括：数据解码器，用于对接收到的数据进行迭代解码以产生解码数据;以及推测性位错误计算器，用于根据解码数据和接收数据计算误码率，同时数据解码器 正在对接收的数据进行解码。 在数据解码器中的每个解码迭代更新误码率。

公开(公告)号：US20140298129A1

公开(公告)日：2014-10-02

申请号：US13852852

申请日：2013-03-28

Applicant: LSI CORPORATION

Inventor： YingQuan Wu ,  Ivana Djurdjevic ,  Alexander Hubris

IPC: H03M13/13

CPC classification number: H03M13/116 ,  H03M13/611 ,  H03M13/616

Abstract: A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H′; and constructing the generator matrix G based on the rearranged parity check matrix H′.

Abstract translation: 公开了一种用于构建发电机矩阵的方法和系统。 该方法包括：接收奇偶校验矩阵H，其中奇偶校验矩阵H包括多个循环子矩阵; 通过列和行排列重排奇偶校验矩阵H以获得重新排列的奇偶校验矩阵H'; 以及基于重新排列的奇偶校验矩阵H'构建生成矩阵G.