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    Systems and methods for data retry using averaging process
    1.
    发明授权
    Systems and methods for data retry using averaging process 有权
    使用平均过程进行数据重试的系统和方法

    公开(公告)号：US09190104B2

    公开(公告)日：2015-11-17

    申请号：US13802627

    申请日：2013-03-13

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Kapil Gaba ,  Yoon L. Liow ,  Xuebin Wu ,  Qi Zuo ,  YuQing Yang ,  Lei Wang

    IPC: G06F17/10 ,  G11B20/10

    CPC classification number: G11B20/10046

    Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for calibration during data processing. As an example, a data processing system is discussed that includes a sample averaging circuit operable to average digital samples from an analog to digital converter circuit over multiple instances of an analog input to yield an X-average output, and a selector circuit operable to select one of the digital samples or the X-average output as a processing output.

    Abstract translation: 实施例涉及用于数据处理的系统和方法，更具体地涉及在数据处理期间用于校准的系统和方法。 作为示例，讨论了一种数据处理系统，其包括采样平均电路，其可操作以在模拟输入的多个实例上平均来自模数转换器电路的数字采样以产生X平均输出，以及可操作以选择 数字样本之一或X平均输出作为处理输出。

    Shift register-based layered low density parity check decoder
    7.
    发明授权
    Shift register-based layered low density parity check decoder 有权
    基于移位寄存器的分层低密度奇偶校验解码器

    公开(公告)号：US09048867B2

    公开(公告)日：2015-06-02

    申请号：US13898685

    申请日：2013-05-21

    Applicant: LSI Corporation

    Inventor： Dan Liu ,  Qi Zuo ,  Chung-Li Wang ,  Zongwang Li ,  Lei Wang

    IPC: H03M13/11 ,  H04L1/00

    CPC classification number: H03M13/1105 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/1174 ,  H03M13/6331 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H04L1/005

    Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

    Abstract translation: 用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。 校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点 基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

    Shift Register-Based Layered Low Density Parity Check Decoder
    8.
    发明申请
    Shift Register-Based Layered Low Density Parity Check Decoder 有权
    基于移位寄存器的分层低密度奇偶校验解码器

    公开(公告)号：US20140351671A1

    公开(公告)日：2014-11-27

    申请号：US13898685

    申请日：2013-05-21

    Applicant: LSI Corporation

    Inventor： Dan Liu ,  Qi Zuo ,  Chung-Li Wang ,  Zongwang Li ,  Lei Wang

    IPC: H03M13/11

    CPC classification number: H03M13/1105 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/1174 ,  H03M13/6331 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H04L1/005

    Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

    Abstract translation: 用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。 校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点 基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。

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