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    SIGNAL AMPLITUDE ADJUSTMENT TO IMPROVE RESOLVER-TO-DIGITAL CONVERTER PERFORMANCE
    1.
    发明申请
    SIGNAL AMPLITUDE ADJUSTMENT TO IMPROVE RESOLVER-TO-DIGITAL CONVERTER PERFORMANCE 有权
    信号幅度调整提高分辨率到数字转换器的性能

    公开(公告)号：US20110140689A1

    公开(公告)日：2011-06-16

    申请号：US12635213

    申请日：2009-12-10

    申请人： Lalinda D. Fernando ,  Michael C.W. Coln

    发明人： Lalinda D. Fernando ,  Michael C.W. Coln

    IPC分类号： G01B7/30

    CPC分类号： G01B7/30

    摘要： An interface system between an RDC and a connected resolver dynamically matches an input range of the RDC to the output range of the resolver's output signals. The interface system may include methods and/or apparatuses to determine the amplitude of sinusoidal input signals presented to the RDC by the resolver and to compare the amplitude against high and low threshold values. A gain control signal may be generated, which may be corrected if the detected amplitude either exceeds the high threshold or falls below the low threshold. The gain control signal may be output to a circuit in the RDC or in the resolver that corrects any mismatch that occurs between the RDC input and the resolver output. For example, the gain control signal may control the amplitude of an excitation signal applied to a primary of the resolver or the gain control signal may be applied to an analog to digital converter at the input of the RDC to control its effective input range.

    摘要翻译： RDC和连接的解析器之间的接口系统动态地将RDC的输入范围与解算器的输出信号的输出范围进行匹配。 接口系统可以包括用于确定由解算器呈现给RDC的正弦输入信号的幅度并且将幅度与高和低阈值进行比较的方法和/或装置。 可以生成增益控制信号，如果检测到的幅度超过高阈值或低于低阈值，则可以校正增益控制信号。 增益控制信号可以被输出到RDC或解析器中的电路，该解算器校正RDC输入和解析器输出之间出现的任何失配。 例如，增益控制信号可以控制施加到旋转变压器的初级的激励信号的幅度，或者增益控制信号可以在RDC的输入处施加到模数转换器，以控制其有效输入范围。

    Serial digital data communication interface
    5.
    发明申请
    Serial digital data communication interface 有权
    串行数字数据通信接口

    公开(公告)号：US20080123790A1

    公开(公告)日：2008-05-29

    申请号：US11903529

    申请日：2007-09-21

    申请人： Michael C.W. Coln ,  Alain Guery

    发明人： Michael C.W. Coln ,  Alain Guery

    IPC分类号： H04L7/00

    CPC分类号： H04L7/10 ,  H04L7/0337 ,  H04L7/041 ,  H04L7/042 ,  H04L7/046

    摘要： A serial protocol and interface for data transmission from a data transmitter 12 to a data receiver 14 where the propagation delay may be up to several clock cycles long and may be varying slowly. The data receiver provides a clock to the data transmitter. A synchronization signal provided by either the receiver or the transmitter initiates a frame of data transmission at a transfer rate controlled by the clock. The synchronization signal coordinates the transmission of a data header followed by a predetermined number of data bits, known as the frame length. The data receiver uses the header bits to determine the times to sample the subsequent data bits. The length of the frame is limited to provide sufficient likelihood the propagation delay line characteristics have not changed enough to cause a bit error. The system resynchronizes at the beginning of each frame.

    摘要翻译： 用于从数据发射器12到数据接收器14的数据传输的串行协议和接口，其中传播延迟可以长达几个时钟周期并且可能缓慢变化。 数据接收器为数据发送器提供时钟。 由接收机或发射机提供的同步信号以由时钟控制的传输速率发起数据传输帧。 同步信号协调数据标题的传输，接着是预定数量的数据位，称为帧长度。 数据接收器使用标题位来确定对后续数据位采样的次数。 帧的长度被限制为提供传播延迟线特性没有足够变化以造成位错误的足够的可能性。 系统在每帧开始时重新同步。