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21 条记录 (耗时 0.061 秒)

    Differential front-end continuous-time sigma-delta ADC using chopper stabilization
    7.
    发明授权
    Differential front-end continuous-time sigma-delta ADC using chopper stabilization 有权
    差分前端连续时间Σ-ΔADC使用斩波稳定

    公开(公告)号：US07193545B2

    公开(公告)日：2007-03-20

    申请号：US11228113

    申请日：2005-09-16

    申请人： Paul John Morrow ,  Maria del Mar Chamarro Marti ,  Colin G. Lyden ,  Mike Dominic Keane ,  Robert W. Adams ,  Richard Thomas O'Brien ,  Paschal Thomas Minogue ,  Hans Johan Olaf Mansson

    发明人： Paul John Morrow ,  Maria del Mar Chamarro Marti ,  Colin G. Lyden ,  Mike Dominic Keane ,  Robert W. Adams ,  Richard Thomas O'Brien ,  Paschal Thomas Minogue ,  Hans Johan Olaf Mansson

    IPC分类号： H03M3/00

    CPC分类号： H03M3/34 ,  H03M3/332 ,  H03M3/424 ,  H03M3/454

    摘要： A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency FS and the chopping switches can operate at FS or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.

    摘要翻译： 多位连续时间Σ-Δ模数转换器（ADC）具有接收模拟输入信号电流的差分输入级。 多位反馈电流数模转换器（IDAC）根据闪存ADC的数字反馈信号产生多电平反馈电流。 积分器具有差分输入，其通过多位IDAC产生的电流与输入信号电流的连续时间积分。 输入级还包括第一偏置电流源和在中等尺度条件下偏置输入级的第二偏置电流源。 第一求和节点连接到第一差分输入线，积分器的第一差分输入和第一输出分支。 第二求和节点连接到第二差分输入线，积分器和第二输出分支的第二差分输入。 一组斩波开关将偏置电流源以第一配置和第二反向配置交替地连接到求和节点。 转换器以频率F S S接收调制器时钟信号，并且斩波开关可以在F S或其二进制细分上工作。 积分放大器也可以斩波稳定。

    Sample and hold apparatus
    8.
    发明授权
    Sample and hold apparatus 有权
    采样和保持设备

    公开(公告)号：US07113116B2

    公开(公告)日：2006-09-26

    申请号：US11045672

    申请日：2005-01-26

    申请人： Robert J. Brewer ,  Colin G. Lyden ,  Michael C. W. Coln

    发明人： Robert J. Brewer ,  Colin G. Lyden ,  Michael C. W. Coln

    IPC分类号： H03M1/00

    CPC分类号： G11C27/026 ,  G11C27/024

    摘要： An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

    摘要翻译： 提供一种采集和平均电路，其中在采样相位期间，采样块4和6中的电容器顺序地连接到输入信号以对其进行采样，然后被隔离以保持样本。 然后将电容器连接到组合/平均布置，使得形成样本值的平均值。

    BATTERY MODULE TESTING
    9.
    发明申请
    BATTERY MODULE TESTING 有权

    公开(公告)号：US20220413054A1

    公开(公告)日：2022-12-29

    申请号：US17822092

    申请日：2022-08-24

    申请人： Shane O'Mahony ,  Joseph Caissie Bush ,  Colin G. Lyden

    发明人： Shane O'Mahony ,  Joseph Caissie Bush ,  Colin G. Lyden

    IPC分类号： G01R31/385 ,  G01R31/36 ,  G01R31/396 ,  H01M10/42 ,  H01M10/48

    摘要： Testing of a battery module can be conducted using monitoring electronics attached to the battery module. Stimulus can be applied to the battery module and removed. After removal of the stimulus, the monitoring electronics can collect signals from the monitoring electronics reflecting parameters of the battery module as it relaxes back to a non-stimulated state. The stimulus can be provided by test equipment or by components of a system in which the battery module, having attached monitoring electronics, is implemented. The monitoring electronics attached to the battery module can provide autonomous recording of signals associated with the battery module that can provide data regarding the status of the battery module or one or more batteries contained in the battery module.

    Amplifier, a residue amplifier, and an ADC including a residue amplifier
    10.
    发明授权
    Amplifier, a residue amplifier, and an ADC including a residue amplifier 有权
    放大器，残留放大器和包括残留放大器的ADC

    公开(公告)号：US09231539B2

    公开(公告)日：2016-01-05

    申请号：US13787065

    申请日：2013-03-06

    申请人： Colin G. Lyden ,  Christopher Peter Hurrell ,  Derek Hummerston

    发明人： Colin G. Lyden ,  Christopher Peter Hurrell ,  Derek Hummerston

    IPC分类号： H03F3/45 ,  H03M1/16

    CPC分类号： H03F3/45076 ,  H03F3/45183 ,  H03M1/164

    摘要： An amplifier, comprising: an input node; an output node; a gain stage having a gain stage inverting input, a gain stage non-inverting input and a gain stage output; a feedback capacitor connected in a signal path between the gain stage output and the gain stage inverting input; a sampling capacitor connected between the input node and the gain stage inverting input, and a controllable impedance in parallel with the feedback capacitor, wherein the controllable impedance is operable to switch between a first impedance state in which it does not affect current flow through the feedback capacitor, and a second impedance state in which it cooperates with the feedback capacitor form a bandwidth limiting circuit.

    摘要翻译： 一种放大器，包括：输入节点; 输出节点; 具有增益级反相输入，增益级非反相输入和增益级输出的增益级; 连接在增益级输出和增益级反相输入之间的信号路径中的反馈电容器; 连接在所述输入节点和所述增益级反相输入端之间的采样电容器，以及与所述反馈电容器并联的可控阻抗，其中所述可控阻抗可操作以在其不影响通过所述反馈的电流的第一阻抗状态之间切换 电容器和与反馈电容器配合的第二阻抗状态形成带宽限制电路。