公开(公告)号：US08778786B1

公开(公告)日：2014-07-15

申请号：US13482394

申请日：2012-05-29

申请人： Lance Scudder ,  Pushkar Ranade ,  Dalong Zhao ,  Teymur Bakhishev ,  Urupattur C. Sridharan ,  Taiji Ema ,  Toshifumi Mori ,  Mitsuaki Hori ,  Junji Oh ,  Kazushi Fujita ,  Yasunobu Torii

发明人： Lance Scudder ,  Pushkar Ranade ,  Dalong Zhao ,  Teymur Bakhishev ,  Urupattur C. Sridharan ,  Taiji Ema ,  Toshifumi Mori ,  Mitsuaki Hori ,  Junji Oh ,  Kazushi Fujita ,  Yasunobu Torii

IPC分类号： H01L21/425 ,  H01L21/336 ,  H01L21/266 ,  H01L21/311

CPC分类号： H01L21/266 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/8239 ,  H01L27/0928

摘要： Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.

摘要翻译： 在晶体管器件元件制造期间在衬底中防止硅损失是通过在制造过程中限制光刻胶掩模和化学氧化物层剥离的机会来实现的。 这可以通过使用在形成和剥离用于将植入区域识别到衬底中的光致抗蚀剂掩模保留在衬底上的保护层来实现。 此外，由于光致抗蚀剂掩模未对准而导致的不期望的返工步骤被消除，或者在器件元件制造过程中不会对来自衬底的硅消耗产生影响。 以这种方式，具有相同操作特性和性能的装置元件可以从批量到大量一致地进行。

公开(公告)号：US08778752B2

公开(公告)日：2014-07-15

申请号：US12938483

申请日：2010-11-03

申请人： Yasunobu Torii

发明人： Yasunobu Torii

IPC分类号： H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/7843

摘要： A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.