公开(公告)号：US08999861B1

公开(公告)日：2015-04-07

申请号：US13469249

申请日：2012-05-11

申请人： Lance Scudder ,  Pushkar Ranade ,  Charles Stager ,  Lucian Shifren ,  Dalong Zhao ,  U.C. Sridharan ,  Michael Duane

发明人： Lance Scudder ,  Pushkar Ranade ,  Charles Stager ,  Lucian Shifren ,  Dalong Zhao ,  U.C. Sridharan ,  Michael Duane

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L21/02205 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/105 ,  H01L29/6659

摘要： A method for fabricating a semiconductor structure so as to have reduced junction leakage is disclosed. The method includes providing substitutional boron in a semiconductor substrate. The method includes preparing the substrate using a pre-amorphization implant and a carbon implant followed by a recrystallization step and a separate defect repair/activation step. Boron is introduced to the pre-amorphized region preferably by ion implantation.

摘要翻译： 公开了一种用于制造半导体结构以减少结漏电的方法。 该方法包括在半导体衬底中提供取代的硼。 该方法包括使用预非晶化植入物和碳注入制备底物，接着进行重结晶步骤和单独的缺陷修复/活化步骤。 优选通过离子注入将硼引入到非晶化区域中。

公开(公告)号：US08883600B1

公开(公告)日：2014-11-11

申请号：US13725152

申请日：2012-12-21

申请人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

发明人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

IPC分类号： H01L21/331 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836

摘要： A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

摘要翻译： 晶体管及其制造方法包括至少部分地形成在沟道层和栅极堆叠下方的半导体衬底中的屏蔽层，栅极堆叠包括在栅极叠层的任一侧上的间隔结构。 晶体管包括沟道层中的浅掺杂稀土漏极区和相对于屏蔽层底部的深度处的深掺杂漏极区，用于减少结漏电流。 还可以包括补偿层以防止背栅控制的损失。

公开(公告)号：US08614128B1

公开(公告)日：2013-12-24

申请号：US13591767

申请日：2012-08-22

申请人： Scott E. Thompson ,  Thomas Hoffmann ,  Lance Scudder ,  U. C. Sridharan ,  Dalong Zhao ,  Pushkar Ranade ,  Michael Duane ,  Paul E. Gregory

发明人： Scott E. Thompson ,  Thomas Hoffmann ,  Lance Scudder ,  U. C. Sridharan ,  Dalong Zhao ,  Pushkar Ranade ,  Michael Duane ,  Paul E. Gregory

IPC分类号： H01L21/8234

CPC分类号： H01L27/1104 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/11 ,  H01L29/0653 ,  H01L29/16

摘要： Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

摘要翻译： 提供了制造半导体器件及其器件的方法。 一种方法包括提供具有第一和第二层的具有半导体表面的衬底，其中半导体表面具有包括第一和第二有源区的多个有源区。 在第一有源区中，第一层是未掺杂层，第二层是高度掺杂的掩膜层。 该方法还包括移除第一层的一部分以减少第一有源区的至少一部分的基本上未掺杂层的厚度，而在第二有源区中没有相应的第一层的厚度减小。 该方法还包括在多个有源区域中形成半导体器件。 在该方法中，基于第一有源区的部分中的衬底所需的阈值电压调整来选择去除第一层的部分。

公开(公告)号：US20140103406A1

公开(公告)日：2014-04-17

申请号：US14133743

申请日：2013-12-19

申请人： Lingquan Wang ,  Teymur Bakhishev ,  Dalong Zhao ,  Pushkar Ranade ,  Sameer Pradhan ,  Thomas Hoffmann ,  Lucian Shifren ,  Lance Scudder

发明人： Lingquan Wang ,  Teymur Bakhishev ,  Dalong Zhao ,  Pushkar Ranade ,  Sameer Pradhan ,  Thomas Hoffmann ,  Lucian Shifren ,  Lance Scudder

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66477 ,  H01L29/6659

摘要： A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.

摘要翻译： 半导体结构由NFET器件和PFET器件形成。 通过掩蔽衬底的PFET器件区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏蔽层上形成未掺杂沟道层，形成NFET器件。 PFET器件类似地通过掩蔽衬底的NFET区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏幕层上形成未掺杂沟道层。 在NFET和PFET器件区域之间形成隔离区以去除在单独外延生长阶段期间发生的任何刻面。 通过原位掺杂外延生长形成屏蔽层，相对于使用离子注入形成屏幕层，实现了结漏电减少。

公开(公告)号：US08637955B1

公开(公告)日：2014-01-28

申请号：US13600647

申请日：2012-08-31

申请人： Lingquan Wang ,  Teymur Bakhishev ,  Dalong Zhao ,  Pushkar Ranade ,  Sameer Pradhan ,  Thomas Hoffmann ,  Lucian Shifren ,  Lance Scudder

发明人： Lingquan Wang ,  Teymur Bakhishev ,  Dalong Zhao ,  Pushkar Ranade ,  Sameer Pradhan ,  Thomas Hoffmann ,  Lucian Shifren ,  Lance Scudder

IPC分类号： H01L29/15 ,  H01L29/167 ,  H01L29/36

CPC分类号： H01L29/78 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66477 ,  H01L29/6659

摘要： A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion, implantation.

摘要翻译： 半导体结构由NFET器件和PFET器件形成。 通过掩蔽衬底的PFET器件区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏蔽层上形成未掺杂沟道层，形成NFET器件。 PFET器件类似地通过掩蔽衬底的NFET区域，通过外延生长和原位掺杂形成屏蔽层，并通过外延生长在屏幕层上形成未掺杂沟道层。 在NFET和PFET器件区域之间形成隔离区以去除在单独外延生长阶段期间发生的任何刻面。 通过通过原位掺杂的外延生长形成屏蔽层，相对于使用离子注入形成屏幕层，实现了结漏电减少。

公开(公告)号：US08569156B1

公开(公告)日：2013-10-29

申请号：US13473403

申请日：2012-05-16

申请人： Lance Scudder ,  Pushkar Ranade ,  Charles Stager ,  Urupattur C. Sridharan ,  Dalong Zhao

发明人： Lance Scudder ,  Pushkar Ranade ,  Charles Stager ,  Urupattur C. Sridharan ,  Dalong Zhao

IPC分类号： H01L21/425 ,  H01L21/336 ,  H01L21/36 ,  H01L21/20

CPC分类号： H01L21/823892 ,  H01L21/02694 ,  H01L21/046 ,  H01L21/26506 ,  H01L21/8213 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66068 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

公开(公告)号：US08778786B1

公开(公告)日：2014-07-15

申请号：US13482394

申请日：2012-05-29

申请人： Lance Scudder ,  Pushkar Ranade ,  Dalong Zhao ,  Teymur Bakhishev ,  Urupattur C. Sridharan ,  Taiji Ema ,  Toshifumi Mori ,  Mitsuaki Hori ,  Junji Oh ,  Kazushi Fujita ,  Yasunobu Torii

发明人： Lance Scudder ,  Pushkar Ranade ,  Dalong Zhao ,  Teymur Bakhishev ,  Urupattur C. Sridharan ,  Taiji Ema ,  Toshifumi Mori ,  Mitsuaki Hori ,  Junji Oh ,  Kazushi Fujita ,  Yasunobu Torii

IPC分类号： H01L21/425 ,  H01L21/336 ,  H01L21/266 ,  H01L21/311

CPC分类号： H01L21/266 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/8239 ,  H01L27/0928

摘要： Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.

摘要翻译： 在晶体管器件元件制造期间在衬底中防止硅损失是通过在制造过程中限制光刻胶掩模和化学氧化物层剥离的机会来实现的。 这可以通过使用在形成和剥离用于将植入区域识别到衬底中的光致抗蚀剂掩模保留在衬底上的保护层来实现。 此外，由于光致抗蚀剂掩模未对准而导致的不期望的返工步骤被消除，或者在器件元件制造过程中不会对来自衬底的硅消耗产生影响。 以这种方式，具有相同操作特性和性能的装置元件可以从批量到大量一致地进行。

公开(公告)号：US20110183079A1

公开(公告)日：2011-07-28

申请号：US12872040

申请日：2010-08-31

申请人： Thomas Jackson ,  Devin A. Mourey ,  Dalong Zhao

发明人： Thomas Jackson ,  Devin A. Mourey ,  Dalong Zhao

IPC分类号： C08F2/46

CPC分类号： C23C16/40 ,  C23C16/45542

摘要： Improved systems, methods and compositions for plasma enhanced atomic layer deposition are herein disclosed. According to one embodiment, a method includes exposing a substrate to a first process material to form a film comprising at least a portion of the first process material at a surface of the substrate. The substrate is exposed to a second process material and the second process material is activated into plasma to initiate a reaction between at least a portion of the first process material and at least a portion of the second process material at the surface of the substrate.

摘要翻译： 本文公开了用于等离子体增强的原子层沉积的改进的系统，方法和组合物。 根据一个实施例，一种方法包括将衬底暴露于第一工艺材料以形成在衬底的表面上包含第一工艺材料的至少一部分的膜。 衬底暴露于第二工艺材料，第二工艺材料被激活成等离子体以引发第一工艺材料的至少一部分与第二工艺材料的至少部分在衬底表面处的反应。