公开(公告)号：US20120223391A1

公开(公告)日：2012-09-06

申请号：US13343078

申请日：2012-01-04

申请人： Kazushi Fujita ,  Taiji Ema ,  Hiroyuki Ogawa

发明人： Kazushi Fujita ,  Taiji Ema ,  Hiroyuki Ogawa

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823892 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film.

摘要翻译： 半导体器件包括：第一晶体管，包括形成在半导体衬底的第一区域中的第一导电类型的第一杂质层;形成在第一杂质层上方的第一外延半导体层;形成在第一外延半导体上方的第一栅极绝缘膜; 以及形成在所述第一栅极绝缘膜上方的第一栅电极，以及形成在所述半导体衬底的第二区域中的包括所述第二导电类型的第二杂质层的第二晶体管，形成在所述第二杂质层上方的第二外延半导体层 并且具有不同于第一外延半导体层的厚度的第二栅极绝缘膜，形成在第二外延半导体层上方并具有与第一栅极绝缘膜相同的膜厚度的第二栅极绝缘膜和形成在第二栅极之上的第二栅电极 绝缘膜。

公开(公告)号：US08063468B2

公开(公告)日：2011-11-22

申请号：US12207922

申请日：2008-09-10

申请人： Kazushi Fujita ,  Ryota Nanjo

发明人： Kazushi Fujita ,  Ryota Nanjo

IPC分类号： H01L23/00 ,  H01L21/762

CPC分类号： H01L27/0207 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor chip, a moisture resistant ring provided in the semiconductor chip and having a chamfered flat part in a position corresponding to a corner of the semiconductor chip, and a first monitor pattern formed inside the moisture resistant ring. At least a part of the first monitor pattern is disposed inside an n-sided polygonal area (n is a natural number which is 4 or higher than 4) situated within the moisture resistant ring, and outside a quadrangular area situated inside the n-sided polygonal area. The n-sided polygonal area has a vertex at least at each of a first end and a second end of the chamfered flat part, and the quadrangular area has a vertex at least at a middle point of the chamfered flat part.

摘要翻译： 半导体器件包括半导体芯片，设置在半导体芯片中的防潮环，并且在与半导体芯片的角部相对应的位置具有倒角平坦部分，以及形成在防潮环内的第一监视器图案。 第一监视器图案的至少一部分设置在位于防潮环内的n侧多边形区域（n为4或高于4的自然数）内，并且位于位于n侧内侧的四边形区域的外侧 多边形区域。 所述n侧多边形区域至少在所述倒角平坦部的第一端和第二端各具有顶点，所述四边形区域至少在所述倒角平坦部的中点处具有顶点。

公开(公告)号：US08294217B2

公开(公告)日：2012-10-23

申请号：US13172224

申请日：2011-06-29

申请人： Taiji Ema ,  Kazushi Fujita ,  Junji Oh

发明人： Taiji Ema ,  Kazushi Fujita ,  Junji Oh

IPC分类号： H01L21/70

CPC分类号： H01L21/823418 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/761 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.

摘要翻译： 半导体器件包括：第一晶体管，包括含有硼或磷的第一杂质层;形成在第一杂质层上方的第一外延层;形成在第一外延层上方的第一栅电极，其间形成有第一栅极绝缘膜， 漏区，以及包含含有硼和碳或砷或锑的第二杂质层的第二晶体管，形成在第二杂质层上方的第二外延层，形成在第二外延层上方的第二栅电极，第二栅极绝缘膜更薄 比其间形成的第一栅极绝缘膜，以及第二源极/漏极区域。

公开(公告)号：US07910957B2

公开(公告)日：2011-03-22

申请号：US12342453

申请日：2008-12-23

申请人： Junichi Mitani ,  Satoshi Nakai ,  Kazushi Fujita

发明人： Junichi Mitani ,  Satoshi Nakai ,  Kazushi Fujita

IPC分类号： H01L23/52

CPC分类号： H01L21/823456 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.

摘要翻译： 半导体器件具有设置在半导体衬底上的第一导电类型的第一和第二有源区，设置在半导体衬底上的第二导电类型的第三和第四有源区，第二和第四有源区的尺寸较大 分别设置为与第一有源区域相邻并且具有第一宽度的第一导电图案，与第二有源区域相邻设置并且具有大于第一宽度的第二宽度的第二导电图案 第三导电图案，其布置成与所述第三有源区相邻并且具有第三宽度; 以及第四导电图案，其布置成与所述第四有源区相邻并且具有小于所述第三宽度的第四宽度。

公开(公告)号：US20100013023A1

公开(公告)日：2010-01-21

申请号：US12500277

申请日：2009-07-09

申请人： Kazushi FUJITA

发明人： Kazushi FUJITA

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

摘要： A semiconductor device includes a first MISFET having a first conduction type channel and formed on a semiconductor substrate; a second MISFET having a second conduction type channel and formed on the semiconductor substrate; a first strain film having a first sign strain that covers a region where the second MISFET is disposed; and a second strain film having a second sign strain that covers a region where the first MISFET is disposed. In the semiconductor device, an edge of the second strain film closer to the second MISFET overlaps with part of the first strain film; and the second strain film at a portion where the second strain film overlaps with the first strain film and at a portion extending from the portion, is thinner than the second strain film at a portion that covers the first MISFET.

摘要翻译： 半导体器件包括具有第一导电型沟道并形成在半导体衬底上的第一MISFET; 具有第二导电型沟道并形成在所述半导体衬底上的第二MISFET; 具有覆盖所述第二MISFET的区域的第一符号应变的第一应变膜; 以及具有覆盖所述第一MISFET的区域的第二符号应变的第二应变膜。 在半导体器件中，更靠近第二MISFET的第二应变膜的边缘与第一应变膜的一部分重叠; 并且第二应变膜在第二应变膜与第一应变膜重叠的部分和从该部分延伸的部分处的第二应变膜在覆盖第一MISFET的部分处比第二应变膜薄。

公开(公告)号：US20090079039A1

公开(公告)日：2009-03-26

申请号：US12207922

申请日：2008-09-10

申请人： Kazushi FUJITA ,  Ryota NANJO

发明人： Kazushi FUJITA ,  Ryota NANJO

IPC分类号： H01L23/58 ,  H01L21/76

CPC分类号： H01L27/0207 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor chip, a moisture resistant ring provided in the semiconductor chip and having a chamfered flat part in a position corresponding to a corner of the semiconductor chip, and a first monitor pattern formed inside the moisture resistant ring. At least a part of the first monitor pattern is disposed inside an n-sided polygonal area (n is a natural number which is 4 or higher than 4) situated within the moisture resistant ring, and outside a quadrangular area situated inside the n-sided polygonal area. The n-sided polygonal area has a vertex at least at each of a first end and a second end of the chamfered flat part, and the quadrangular area has a vertex at least at a middle point of the chamfered flat part.

摘要翻译： 半导体器件包括半导体芯片，设置在半导体芯片中的防潮环，并且在与半导体芯片的角部相对应的位置具有倒角平坦部分，以及形成在防潮环内的第一监视器图案。 第一监视器图案的至少一部分设置在位于防潮环内的n侧多边形区域（n为4或高于4的自然数）内，并且位于位于n侧内侧的四边形区域的外侧 多边形区域。 所述n侧多边形区域至少在所述倒角平坦部的第一端和第二端各具有顶点，所述四边形区域至少在所述倒角平坦部的中点处具有顶点。

公开(公告)号：US08778786B1

公开(公告)日：2014-07-15

申请号：US13482394

申请日：2012-05-29

申请人： Lance Scudder ,  Pushkar Ranade ,  Dalong Zhao ,  Teymur Bakhishev ,  Urupattur C. Sridharan ,  Taiji Ema ,  Toshifumi Mori ,  Mitsuaki Hori ,  Junji Oh ,  Kazushi Fujita ,  Yasunobu Torii

发明人： Lance Scudder ,  Pushkar Ranade ,  Dalong Zhao ,  Teymur Bakhishev ,  Urupattur C. Sridharan ,  Taiji Ema ,  Toshifumi Mori ,  Mitsuaki Hori ,  Junji Oh ,  Kazushi Fujita ,  Yasunobu Torii

IPC分类号： H01L21/425 ,  H01L21/336 ,  H01L21/266 ,  H01L21/311

CPC分类号： H01L21/266 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/8239 ,  H01L27/0928

摘要： Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.

摘要翻译： 在晶体管器件元件制造期间在衬底中防止硅损失是通过在制造过程中限制光刻胶掩模和化学氧化物层剥离的机会来实现的。 这可以通过使用在形成和剥离用于将植入区域识别到衬底中的光致抗蚀剂掩模保留在衬底上的保护层来实现。 此外，由于光致抗蚀剂掩模未对准而导致的不期望的返工步骤被消除，或者在器件元件制造过程中不会对来自衬底的硅消耗产生影响。 以这种方式，具有相同操作特性和性能的装置元件可以从批量到大量一致地进行。

公开(公告)号：US08592278B2

公开(公告)日：2013-11-26

申请号：US13177337

申请日：2011-07-06

申请人： Kazushi Fujita ,  Junji Oh

发明人： Kazushi Fujita ,  Junji Oh

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The method of manufacturing the semiconductor device includes forming a trench to be an alignment mark in a semiconductor substrate, forming a mask film exposing a region to be a device isolation region and covering a region to be a device region by aligning with the alignment mark above the semiconductor substrate with the trench formed in, anisotropically etching the semiconductor substrate with the mask film as a mask to form a device isolation trench in the region to be the device isolation region of the semiconductor substrate, and burying the device isolation trench by an insulating film to form a device isolation insulating film. In forming the trench, the trench is formed in a depth which is smaller than a depth equivalent to a thickness of the mask film.

摘要翻译： 制造半导体器件的方法包括在半导体衬底中形成作为对准标记的沟槽，形成将区域暴露为器件隔离区域的掩模膜，并通过与上述对准标记对准来覆盖作为器件区域的区域 形成有沟槽的半导体衬底，以掩模膜为掩膜，各向异性蚀刻半导体衬底，以在该半导体衬底的器件隔离区域中形成器件隔离沟槽，并通过绝缘材料掩埋器件隔离沟槽 膜形成器件隔离绝缘膜。 在形成沟槽时，沟槽的形成深度小于与掩模膜的厚度相当的深度。

公开(公告)号：US20120080759A1

公开(公告)日：2012-04-05

申请号：US13170762

申请日：2011-06-28

申请人： Taiji Ema ,  Kazushi Fujita

发明人： Taiji Ema ,  Kazushi Fujita

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/7833

摘要： A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region. A second transistor includes a second impurity layer of the first conduction type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and being thinner than the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer, a second gate electrode formed above the second gate insulating film, and second source/drain regions of the second conduction type formed in the second epitaxial semiconductor layer and in the semiconductor substrate in the second region.

摘要翻译： 第一晶体管包括形成在半导体衬底的第一区域中的第一导电类型的第一杂质层，形成在第一杂质层上方的第一外延半导体层，形成在第一外延半导体层上方的第一栅极绝缘膜， 形成在第一栅极绝缘膜上方的栅极电极和形成在第一外延半导体层中的第二导电类型的第一源极/漏极区域和在第一区域中的半导体衬底中。 第二晶体管包括形成在半导体衬底的第二区域中的第一导电类型的第二杂质层，形成在第二杂质层上方并且比第一外延半导体层薄的第二外延半导体层，形成第二栅极绝缘膜 在第二外延半导体层上方形成第二栅极，形成在第二栅极绝缘膜上方的第二栅极电极以及形成在第二外延半导体层中的第二导电类型的第二源极/漏极区域和在第二区域中的半导体衬底中。

公开(公告)号：US20120080754A1

公开(公告)日：2012-04-05

申请号：US13172224

申请日：2011-06-29

申请人： Taiji Ema ,  Kazushi Fujita ,  Junji Oh

发明人： Taiji Ema ,  Kazushi Fujita ,  Junji Oh

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L21/823418 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/761 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.

摘要翻译： 半导体器件包括：第一晶体管，包括含有硼或磷的第一杂质层;形成在第一杂质层上方的第一外延层;形成在第一外延层上方的第一栅电极，其间形成有第一栅极绝缘膜， 漏区，以及包含含有硼和碳或砷或锑的第二杂质层的第二晶体管，形成在第二杂质层上方的第二外延层，形成在第二外延层上方的第二栅电极，第二栅极绝缘膜更薄 比其间形成的第一栅极绝缘膜，以及第二源极/漏极区域。