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1.发明授权Fault tolerant extended processing complex for redundant nonvolatile file caching 失效用于冗余非易失性文件缓存的容错扩展处理复杂
公开(公告)号：US5809543A
公开(公告)日：1998-09-15
申请号：US745111
申请日：1996-11-07
CPC分类号： G06F11/1666 , G06F11/20 , G06F11/2015 , G06F12/084 , G06F12/0866
摘要： An outboard file cache extended processing complex for use with a host data processing system for providing closely coupled file caching capability is described. Data movers at the host provide the hardware interface to the outboard file cache, provide the formatting of file data and commands, and control the reading and writing of data from the extended processing complex. Host interface adapters receive file access commands sent from the data movers and provide cache access control. Directly coupled fiber optic links couple each of the data movers to the associated one of the host interface adapters and from the nonvolatile memory. A nonvolatile memory to store redundant copies of the cached file data is described. A system interface including bidirectional bus structures and index processors that control the routing of data signals, provides control of storage and retrieval of file cache data derived from host interface adapters and from the nonvolatile memory. Multiple power domains are described together with independent clock distribution within each power domain. The independent clock distribution sources are synchronized with each other. A system for fault tolerant redundant storage of file cache data redundantly in at least two portions of the nonvolatile file cache storage is described.
摘要翻译： 描述了用于提供紧密耦合的文件缓存能力的主机数据处理系统的外部文件缓存扩展处理复合体。 主机上的数据移动器为外部文件缓存提供硬件接口，提供文件数据和命令的格式化，并控制从扩展处理复合体读取和写入数据。 主机接口适配器接收从数据移动器发送的文件访问命令，并提供缓存访问控制。 直接耦合的光纤链路将每个数据移动器耦合到相关的一个主机接口适配器和非易失性存储器。 描述用于存储缓存的文件数据的冗余副本的非易失性存储器。 包括控制数据信号路由的双向总线结构和索引处理器的系统接口提供对从主机接口适配器和非易失性存储器导出的文件缓存数据的存储和检索的控制。 多个功率域在每个功率域内与独立时钟分配一起进行描述。 独立的时钟分配源彼此同步。 描述了在非易失性文件高速缓存存储器的至少两个部分中冗余地冗余存储文件高速缓存数据的系统。
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公开(公告)号：US5495589A
公开(公告)日：1996-02-27
申请号：US173429
申请日：1993-12-23
IPC分类号： G06F11/20 , G06F13/00 , G06F15/173 , G06F15/76
CPC分类号： G06F15/17381
摘要： A computer architecture for providing enhanced reliability by coupling a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are bi-directional busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures to the desired destination. The HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. The either increase or decrease the number of HUB elements and streets can be.
摘要翻译： 一种用于通过将称为街道的多个公共共享总线与多个称为HUB的智能交换元件耦合来提供增强的可靠性的计算机体系结构。 街道是用于在HUB元件之间传输数据的双向总线。 HUB元素能够将街道结构上的数据引导到所需的目的地。 HUB元件具有内置优先级方案，用于允许在低优先级数据之前传输高优先级数据。 可以增加或减少HUB元素和街道的数量。
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公开(公告)号：US5471482A
公开(公告)日：1995-11-28
申请号：US223435
申请日：1994-04-05
申请人： Larry L. Byers , Donald W. Mackenthun , Philip J. Fye , Gerald J. Maciona , Jeff A. Engel , Ferris T. Price, deceased , Dale K. Seppa
发明人： Larry L. Byers , Donald W. Mackenthun , Philip J. Fye , Gerald J. Maciona , Jeff A. Engel , Ferris T. Price, deceased , Dale K. Seppa
CPC分类号： G11C29/10
摘要： A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.
摘要翻译： 一种全面测试嵌入式RAM设备的方法和用于检测嵌入式RAM设备中的任何单元是否具有缓慢的写入恢复时间的装置。 本发明的优选方式利用内置的自检（BIST）技术来测试VLSI设备内的嵌入式RAM。 根据本发明，对嵌入式RAM设备执行修改后的5N行进测试序列。 修改后的5N March测试序列是一种在可编程硬件中实现的简单算法，具有确保嵌入式RAM设备功能并满足恢复时间要求的能力。 本发明的优选方式是在VLSI设备在卡组合中使用之前，使用该算法来确定嵌入式RAM是否正常工作。 但是，这种方法也可以在卡组合后使用来监视嵌入式RAM的完整性。
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4.发明授权Glitch free clock start/stop control circuit for outputting a single clock signal and a single sync signal from a plurality of sync signal inputs and a plurality of clock signal inputs 失效无毛刺时钟启动/停止控制电路，用于从多个同步信号输入和多个时钟信号输入端输出单个时钟信号和单个同步信号
公开(公告)号：US5574753A
公开(公告)日：1996-11-12
申请号：US180896
申请日：1994-01-12
CPC分类号： G06F1/12 , G06F11/1604 , H02J9/06 , H04J3/0688 , G06F11/20 , H04L2007/047
摘要： A glitch free clock switching circuit which produces a predictable and specifiable number of clock pulses to the system elements when switching between clock signals, even during full operation. In addition, the present invention has the capability of only switching between clocks at times that coincides with every Nth clock cycle. This is important in various types of computers systems including high reliability systems because it results in a clock switching circuit which can provide a clock signal which remains consistent throughout the computer system even in light of multiple hardware failures.
摘要翻译： 无毛刺时钟切换电路，即使在完全操作期间切换时钟信号之间，也可向系统元件产生可预测且可指定数量的时钟脉冲。 此外，本发明具有仅在与第N个时钟周期一致的时刻切换时钟的能力。 这在包括高可靠性系统的各种类型的计算机系统中是重要的，因为它导致时钟切换电路，其可以提供即使在多个硬件故障的情况下仍然在整个计算机系统中保持一致的时钟信号。
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5.发明授权Fault tolerant apparatus and method for maintaining one or more queues that are shared by multiple processors 失效用于维护由多个处理器共享的一个或多个队列的容错装置和方法
公开(公告)号：US5649092A
公开(公告)日：1997-07-15
申请号：US583765
申请日：1996-01-11
CPC分类号： G06F11/2043 , G06F11/203 , G06F11/2035
摘要： The disclosure relates to a high performance fault tolerant queuing system. Multiple processors share access to one or more queues which are stored in an addressable memory. A storage controller provides general access to the addressable memory and includes queue functions for maintaining the queues. Queue access is provided in a first-come/first-served basis. In addition to the get and put queue functions, queue control within the storage control saves a queue item which is read from the queue in a location in the addressable memory which is associated with the processor making a get request, thereby alleviating the requesting processor from having to save the queue item.
摘要翻译： 本公开涉及高性能容错排队系统。 多个处理器共享访问存储在可寻址存储器中的一个或多个队列。 存储控制器提供对可寻址存储器的一般访问，并且包括用于维护队列的队列功能。 队列访问以先到先得的方式提供。 除了获取和放置队列功能之外，存储控制器内的队列控制还保存了一个队列项目，该队列项目可从与队列相关联的可寻址存储器中的一个位置从队列中读取，从而缓解请求处理器 必须保存队列项。
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公开(公告)号：US5463644A
公开(公告)日：1995-10-31
申请号：US975381
申请日：1992-11-13
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F11/1028
摘要： A memory system providing capability for correction of multiple bit errors. The storage elements of the memory system are divided into four-bit nibbles, wherein storage of a single 32-word requires access to eight separate storage elements. A ninth storage element stores a four-bit error syndrome. All nine storage elements have single bit error correction/multiple bit error detection. All single bit errors are corrected directly within the individual storage element. Multiple bit errors within a single storage element are signaled to the interface controller which corrects the error using the stored four-bit error syndrome.
摘要翻译： 一种提供校正多位错误能力的存储系统。 存储器系统的存储元件被分成四位半字节，其中单个32字的存储需要访问八个单独的存储元件。 第九存储元件存储四位错误综合征。 所有九个存储元件都具有单位错误校正/多位错误检测。 所有单个位错误在单独存储元件内直接校正。 单个存储元件中的多位错误被发送到接口控制器，该接口控制器使用存储的四位错误综合来校正错误。
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