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公开(公告)号：US5495589A
公开(公告)日：1996-02-27
申请号：US173429
申请日：1993-12-23
IPC分类号： G06F11/20 , G06F13/00 , G06F15/173 , G06F15/76
CPC分类号： G06F15/17381
摘要： A computer architecture for providing enhanced reliability by coupling a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are bi-directional busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures to the desired destination. The HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. The either increase or decrease the number of HUB elements and streets can be.
摘要翻译： 一种用于通过将称为街道的多个公共共享总线与多个称为HUB的智能交换元件耦合来提供增强的可靠性的计算机体系结构。 街道是用于在HUB元件之间传输数据的双向总线。 HUB元素能够将街道结构上的数据引导到所需的目的地。 HUB元件具有内置优先级方案，用于允许在低优先级数据之前传输高优先级数据。 可以增加或减少HUB元素和街道的数量。
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公开(公告)号：US5471482A
公开(公告)日：1995-11-28
申请号：US223435
申请日：1994-04-05
申请人： Larry L. Byers , Donald W. Mackenthun , Philip J. Fye , Gerald J. Maciona , Jeff A. Engel , Ferris T. Price, deceased , Dale K. Seppa
发明人： Larry L. Byers , Donald W. Mackenthun , Philip J. Fye , Gerald J. Maciona , Jeff A. Engel , Ferris T. Price, deceased , Dale K. Seppa
CPC分类号： G11C29/10
摘要： A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.
摘要翻译： 一种全面测试嵌入式RAM设备的方法和用于检测嵌入式RAM设备中的任何单元是否具有缓慢的写入恢复时间的装置。 本发明的优选方式利用内置的自检（BIST）技术来测试VLSI设备内的嵌入式RAM。 根据本发明，对嵌入式RAM设备执行修改后的5N行进测试序列。 修改后的5N March测试序列是一种在可编程硬件中实现的简单算法，具有确保嵌入式RAM设备功能并满足恢复时间要求的能力。 本发明的优选方式是在VLSI设备在卡组合中使用之前，使用该算法来确定嵌入式RAM是否正常工作。 但是，这种方法也可以在卡组合后使用来监视嵌入式RAM的完整性。
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3.发明授权Fault tolerant extended processing complex for redundant nonvolatile file caching 失效用于冗余非易失性文件缓存的容错扩展处理复杂
公开(公告)号：US5809543A
公开(公告)日：1998-09-15
申请号：US745111
申请日：1996-11-07
CPC分类号： G06F11/1666 , G06F11/20 , G06F11/2015 , G06F12/084 , G06F12/0866
摘要： An outboard file cache extended processing complex for use with a host data processing system for providing closely coupled file caching capability is described. Data movers at the host provide the hardware interface to the outboard file cache, provide the formatting of file data and commands, and control the reading and writing of data from the extended processing complex. Host interface adapters receive file access commands sent from the data movers and provide cache access control. Directly coupled fiber optic links couple each of the data movers to the associated one of the host interface adapters and from the nonvolatile memory. A nonvolatile memory to store redundant copies of the cached file data is described. A system interface including bidirectional bus structures and index processors that control the routing of data signals, provides control of storage and retrieval of file cache data derived from host interface adapters and from the nonvolatile memory. Multiple power domains are described together with independent clock distribution within each power domain. The independent clock distribution sources are synchronized with each other. A system for fault tolerant redundant storage of file cache data redundantly in at least two portions of the nonvolatile file cache storage is described.
摘要翻译： 描述了用于提供紧密耦合的文件缓存能力的主机数据处理系统的外部文件缓存扩展处理复合体。 主机上的数据移动器为外部文件缓存提供硬件接口，提供文件数据和命令的格式化，并控制从扩展处理复合体读取和写入数据。 主机接口适配器接收从数据移动器发送的文件访问命令，并提供缓存访问控制。 直接耦合的光纤链路将每个数据移动器耦合到相关的一个主机接口适配器和非易失性存储器。 描述用于存储缓存的文件数据的冗余副本的非易失性存储器。 包括控制数据信号路由的双向总线结构和索引处理器的系统接口提供对从主机接口适配器和非易失性存储器导出的文件缓存数据的存储和检索的控制。 多个功率域在每个功率域内与独立时钟分配一起进行描述。 独立的时钟分配源彼此同步。 描述了在非易失性文件高速缓存存储器的至少两个部分中冗余地冗余存储文件高速缓存数据的系统。
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公开(公告)号：US5422915A
公开(公告)日：1995-06-06
申请号：US172661
申请日：1993-12-23
CPC分类号： G06F11/1604 , G06F1/12 , H02J9/06 , G06F11/20 , H04J3/0688 , Y10T307/62
摘要： A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop. Error recovery circuitry monitors for proper synchronization of the synchronized clock signals, and provides for automatic or manual error recovery upon detection of a synchronization error. A single phase synchronized clock signal is generated to minimize synchronization complexities, and circuitry exists at the circuit loads to generate multiple phase enable signals to emulate a multiple phase clock.
摘要翻译： 一种用于向多个电路负载提供同步时钟信号的容错多相时钟分配系统。 多个电隔离的电源域由冗余的交流和直流电源电路供电，以确保在交流或直流电源电路部分故障时持续运行。 来自多个电源域的多个振荡器被同步以产生一组同时同步的时钟信号。 然后由选择电路和选择控制电路选择来自该组的多个同步时钟信号，并分配给需要同步同步的多个电路负载。 振荡器电路，同步电路，选择电路和分配电路都以冗余形式提供，使得任何电路的部分故障不会导致系统停止。 错误恢复电路监视同步时钟信号的正确同步，并在检测到同步错误时提供自动或手动错误恢复。 生成单相同步时钟信号以最小化同步复杂度，并且在电路负载处存在电路以产生多相启动信号以仿真多相时钟。
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公开(公告)号：US5664089A
公开(公告)日：1997-09-02
申请号：US589793
申请日：1996-01-22
CPC分类号： G06F11/1666 , G06F11/1415 , G11C29/74 , G06F11/0754 , G06F11/20
摘要： A power loss detection and recovery circuit for providing continued memory operations upon loss of a supply voltage. Multiple independent power domains, each of which provides an electrically isolated supply voltage, are used to provide power to redundant memory circuitry. A loss of voltage or a degenerative voltage within a power domain is detected, and circuitry residing on a different operational power domain provides recovery operations to allow continued memory activity within that operational power domain. The memories residing in an adjacent pair of power domains redundant, and are therefore written to and read from simultaneously, and circuitry within an operational power domain will prevent further reading of data from the memory residing in a failed power domain, and will also prevent further writing of data to the memory residing in the failed power domain upon recognition of a failed supply voltage within a power domain.
摘要翻译： 一种功率损耗检测和恢复电路，用于在电源电压丢失时提供持续的存储器操作。 多个独立的电源域（每个都提供电隔离的电源电压）用于为冗余存储器电路提供电力。 检测到功率域内的电压损耗或退化电压，并且驻留在不同操作功率域的电路提供恢复操作，以允许在该操作功率域内的持续存储器活动。 驻留在相邻电源域对中的存储器是冗余的，并且因此被写入并被同时读取，并且操作功率域内的电路将阻止来自驻留在故障功率域中的存储器的数据的进一步读取，并且还将进一步防止 在识别出功率域内的故障电源电压时，将数据写入存在于故障电源域中的存储器。
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6.发明授权Method and system for using an external bus controller in embedded disk controllers 有权在嵌入式磁盘控制器中使用外部总线控制器的方法和系统公开(公告)号：US07853747B2
公开(公告)日：2010-12-14
申请号：US11803458
申请日：2007-05-15
IPC分类号： G06F13/14
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： An embedded disk controller comprises a first processor in communication with a first bus and a second processor in communication with a second bus. An external bus controller (“EBC”) is located on the embedded disk controller, is coupled to an external bus and to at least one of the first bus and the second bus, and manages a plurality of memory devices external to the embedded disk controller via the external bus. A first one of the plurality of memory devices has at least one of different timing characteristics and a different data width than a second one of the plurality of memory devices.
摘要翻译： 嵌入式盘控制器包括与第一总线通信的第一处理器和与第二总线通信的第二处理器。 外部总线控制器（“EBC”）位于嵌入式磁盘控制器上，耦合到外部总线和第一总线和第二总线中的至少一个，并管理嵌入式磁盘控制器外部的多个存储器件 通过外部总线。 多个存储器件中的第一个具有与多个存储器件中的第二个不同的定时特性和不同数据宽度中的至少一个。
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公开(公告)号：US07080188B2
公开(公告)日：2006-07-18
申请号：US10385022
申请日：2003-03-10
申请人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
发明人： Larry L. Byers , Paul B. Ricci , Joseph G. Kriscunas , Joseba M. Desubijana , Gary R. Robeck , Michael R. Spaur , David M. Purdham
CPC分类号： G06F3/0674 , G06F3/0626 , G06F3/0658 , G06F2213/0038
摘要： A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.
摘要翻译： 提供了一种嵌入式磁盘控制器的系统。 该系统包括可操作地耦合到高性能总线的第一主处理器; 操作地耦合到外围总线的第二处理器; 高性能和外设总线之间的接口桥; 外部总线控制器，耦合到高性能总线，并通过外部总线接口可操作地耦合到外部设备; 中断控制器模块，其可以向第一主处理器产生快速中断; 耦合到高性能和外围总线的历史模块，用于监视总线活动; 以及伺服控制器，其通过伺服控制器接口耦合到第二处理器，并向第二处理器提供实时伺服控制器信息。 第二处理器可以是通过接口可操作地耦合到第一主处理器的数字信号处理器。
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8.发明授权Method and apparatus for locally generating addressing information for a memory access 失效用于本地生成用于存储器访问的寻址信息的方法和装置
公开(公告)号：US5784712A
公开(公告)日：1998-07-21
申请号：US396677
申请日：1995-03-01
CPC分类号： G06F9/30043 , G06F13/1631 , G06F9/345 , G06F9/3861
摘要： A method and apparatus for efficiently reading or writing a number of successive address locations within a memory. In an exemplary embodiment, a processor or the like may not be required to provide an address to a memory unit for each read and/or write operation when successive address locations are accessed. That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit. The subsequent addresses may be automatically generated by an automatic-increment block.
摘要翻译： 一种用于有效地读取或写入存储器内的多个连续地址位置的方法和装置。 在示例性实施例中，当访问连续的地址位置时，可能不需要处理器等来为每个读取和/或写入操作向存储器单元提供地址。 也就是说，对于访问连续地址位置的多个存储器访问，处理器等可以提供初始地址，但此后可能不需要向存储器单元提供后续地址。 随后的地址可以由自动增量块自动生成。
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9.发明授权Method and apparatus for providing fault detection to a bus within a computer system 失效用于向计算机系统内的总线提供故障检测的方法和装置
公开(公告)号：US5784393A
公开(公告)日：1998-07-21
申请号：US396680
申请日：1995-03-01
申请人： Larry L. Byers , Gary R. Robeck , Ronald W. Splett
发明人： Larry L. Byers , Gary R. Robeck , Ronald W. Splett
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： A method and apparatus for providing fault detection to a corresponding bus when one or more of the users connected to the bus does not have a fault detection capability provided therein. Further, the present invention may provide a method and apparatus for performing fault detection on a corresponding bus when the width of the bus is insufficient to accommodate a number of parity bits. In an exemplary embodiment, a selected one of the number of users may validate all bus transmissions via a number of transceivers, regardless of which user has a fault detection capability provided therein. In another exemplary embodiment of the present invention, a transmitting user may provide a data word and a number of corresponding parity bits. The transmitting user may provide the data word to the bus while storing the corresponding number of parity bits therein. The data word may be provided back to the transmitting user via the corresponding transceivers wherein the transmitting user may check the data word against the number of parity bits previously generated by the transmitting user.
摘要翻译： 当连接到总线的一个或多个用户不具有其中提供的故障检测能力时，向相应总线提供故障检测的方法和装置。 此外，本发明可以提供一种用于当总线的宽度不足以容纳多个奇偶校验位时在相应总线上执行故障检测的方法和装置。 在示例性实施例中，所选择的一个用户可以经由多个收发器验证所有总线传输，而不管哪个用户具有其中提供的故障检测能力。 在本发明的另一示例性实施例中，发送用户可以提供数据字和多个对应的奇偶校验位。 发送用户可以在存储相应数量的奇偶校验位的同时向总线提供数据字。 数据字可以经由相应的收发器提供给发送用户，其中发送用户可以根据发送用户先前生成的奇偶校验位的数量来检查数据字。
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10.发明授权Method and apparatus for isolating an error within a computer system that transfers data via an interface device 失效用于隔离通过接口设备传送数据的计算机系统内的错误的方法和装置
公开(公告)号：US5680537A
公开(公告)日：1997-10-21
申请号：US396678
申请日：1995-03-01
CPC分类号： G06F11/2268
摘要： A method and apparatus for isolating an error in a system having a controller or the like which access a user via an interface device. The controller or the like may be coupled to the interface device via a first bus and the interface device may be coupled to the user via a second bus. The controller or the like may detect an error in a data transfer from the user to the controller via the interface device, and may isolate the error to the second bus/interface device or the first bus/controller. This up-front error isolation may reduce the amount of analysis required by a service technician after a corresponding PC board or the like is removed from the system, thereby reducing the cost thereof.
摘要翻译： 一种用于隔离具有通过接口设备访问用户的控制器等的系统中的错误的方法和装置。 控制器等可以经由第一总线耦合到接口设备，并且接口设备可以经由第二总线耦合到用户。 控制器等可以通过接口设备检测从用户到控制器的数据传输中的错误，并且可以将错误与第二总线/接口设备或第一总线/控制器隔离。 这种前期错误隔离可以减少在从系统移除相应的PC板等之后服务技术人员所需的分析量，从而降低其成本。
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