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1.发明授权
公开(公告)号：US5995080A
公开(公告)日：1999-11-30
申请号：US668199
申请日：1996-06-21
CPC分类号： H04N19/577 , H04N19/126 , H04N19/14 , H04N19/176 , H04N19/177 , H04N19/42 , H04N19/51 , H04N19/61 , H04N19/146 , H04N19/152 , Y10S707/99942
摘要： An apparatus and method a method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and thereby provide a more appealing output image.
摘要翻译： 提供了一种用于执行双程实时视频压缩的方法的装置和方法。 用软件确定诸如编码和量化值之类的战术决策，而在硬件中执行功能执行步骤。 通过适当地分配软件和硬件之间的任务，利用每种类型的处理的优点，同时最小化硬件复杂性和数据传输要求。 允许压缩单元实时操作的一个关键概念是架构和流水线均允许B帧被执行无序。 通过缓冲B帧，可以执行双遍运动估计技术，以根据帧的要求定制比特使用，从而提供更有吸引力的输出图像。
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公开(公告)号：US5968153A
公开(公告)日：1999-10-19
申请号：US170812
申请日：1998-10-13
CPC分类号： G06F13/28
摘要： A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.
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公开(公告)号：US5884050A
公开(公告)日：1999-03-16
申请号：US668200
申请日：1996-06-21
CPC分类号： G06F13/28
摘要： A method and apparatus for maximizing the performance of DMA transfers over a PCI.TM. bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality, Back Up register functionality, Gather/Scatter mapping, a method for minimization of PIO writes, Read Semaphore functionality, a method for servicing of DMA transfers during FMU latency periods, Valid bit functionality, high and low water thresholds, and re-usable page tables.
摘要翻译： 提供了一种用于通过PCI TM总线最大化DMA传输的性能的方法和装置，其包括每通道重试计数，双缓冲器管理，等待启用功能，备份寄存器功能，收集/散布映射，最小化 PIO写入，读取信号量功能，一种在FMU等待时间段期间为DMA传输提供服务的方法，有效位功能，高低阈值和可重复使用的页表。
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4.发明申请公开(公告)号：US20090024804A1
公开(公告)日：2009-01-22
申请号：US12207476
申请日：2008-09-09
IPC分类号： G06F12/10
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
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公开(公告)号：US07107201B2
公开(公告)日：2006-09-12
申请号：US09941952
申请日：2001-08-29
CPC分类号： G06F17/5022
摘要： Simulating a logic design having combinatorial logic and state logic includes representing the combinatorial logic and the state logic using separate graphic elements, identifying clock domains for the combinatorial logic and the state logic using the separate graphic elements, generating computer code that simulates operation of portions of the logic design, the computer code being generated based on the clock domains, and associating the computer code with graphic elements that correspond to the portions of the logic design.
摘要翻译： 模拟具有组合逻辑和状态逻辑的逻辑设计包括使用分离的图形元素表示组合逻辑和状态逻辑，识别用于组合逻辑的时钟域和使用分离的图形元素的状态逻辑，生成计算机代码，其模拟部分的操作 逻辑设计，基于时钟域产生的计算机代码，以及将计算机代码与对应于逻辑设计的部分的图形元素相关联。
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公开(公告)号：US07093224B2
公开(公告)日：2006-08-15
申请号：US09941158
申请日：2001-08-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.
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公开(公告)号：US07073156B2
公开(公告)日：2006-07-04
申请号：US09941519
申请日：2001-08-29
CPC分类号： G06F17/5045
摘要： A circuit design parameter file is maintained for a circuit being designed by a circuit designer. This circuit design parameter file specifies a physical characteristic of the circuit. A design environment is monitored to detect the addition of a circuitry component to the circuit and a component design parameter file that specifies at least one design parameter for that added circuitry component is accessed. The circuit design parameter file is updated based on the design parameter(s) included in the component design parameter file. The circuit designer is provided with feedback concerning the physical characteristic of the circuit being designed.
摘要翻译： 为由电路设计者设计的电路维护电路设计参数文件。 该电路设计参数文件指定电路的物理特性。 监视设计环境以检测电路组件到电路的添加，并且访问指定所添加的电路组件的至少一个设计参数的组件设计参数文件。 电路设计参数文件根据组件设计参数文件中包含的设计参数进行更新。 电路设计人员提供有关正在设计的电路的物理特性的反馈。
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公开(公告)号：US06983350B1
公开(公告)日：2006-01-03
申请号：US09387109
申请日：1999-08-31
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
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9.发明授权Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture 失效采用智能逻辑模型来实现简洁的逻辑表示，以便设计描述清晰，并能快速设计公开(公告)号：US06721925B2
公开(公告)日：2004-04-13
申请号：US10025193
申请日：2001-12-18
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： Representing a logic device generally includes creating a model of a logic device, where the model represents a collection of variants of the logic device. A representation of the model may be used in a logic design and a particular variant of the logic device may be selected automatically based on connections made to the representation. Connection errors may be detected automatically and a first indication may be displayed automatically when the connection errors are detected. A second indication that differs from the first indication may be displayed automatically when the connection errors are corrected.
摘要翻译： 代表逻辑设备通常包括创建逻辑设备的模型，其中模型表示逻辑设备的变体的集合。 可以在逻辑设计中使用该模型的表示，并且可以基于对表示形成的连接来自动选择逻辑设备的特定变体。 可以自动检测连接错误，并且当检测到连接错误时可以自动显示第一指示。 当修正连接错误时，可以自动显示与第一指示不同的第二指示。
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10.发明授权
公开(公告)号：US5119483A
公开(公告)日：1992-06-02
申请号：US221944
申请日：1988-07-20
CPC分类号： G06F9/3867 , G06F9/26 , G06F9/30149 , G06F9/3863 , G06F12/10 , Y10S707/99939
摘要： To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information. A microsequencer issues a series of microinstructions for each specifier or operation having been decoded, and also issues a series of microinstructions in a fault routine when a fault occurs. The microsequencer is also provided with a state silo so that the normal sequence of microinstruction execution is resumed when the fault is corrected.
摘要翻译： 为了减少纠正故障所需的处理时间，流水线处理器的指令解码段和第一执行段被提供有在正常指令执行期间操作的“状态仓”以保存足够量的状态信息以立即重启 指令解码器段和第一执行段，通过重新加载已经存储在状态列表中的状态信息。 例如，状态孤岛包括由校正故障期间被禁止的公共时钟信号计时的寄存器队列。 当故障被纠正时，多路复用器从相应流水线段使用的筒仓中选择状态信息。 在优选实施例中，指令解码器段将可变长度宏指令解码为操作数说明符和在指定符上执行的操作。 当新的操作数说明符或操作被解码时，第一执行段接收控制信息，否则保持先前接收到的控制信息。 微定序器为每个说明符或操作已经解码了一系列微指令，并且在出现故障时也会在故障程序中发出一系列微指令。 微定序器还设置有状态仓，使得当故障被校正时，微指令执行的正常序列被恢复。
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