-
公开(公告)号：US06351814B1
公开(公告)日：2002-02-26
申请号：US09358687
申请日：1999-07-21
IPC分类号： G06K1906
CPC分类号： G06F21/76 , G06F12/1408 , G06F2211/007 , G06F2221/2107
摘要： A field programmable gate array (FPGA) and a decryption circuit are implemented within a common integrated circuit (IC) or within separate ICs enclosed within a common IC package. The decryption circuit decrypts an input FPGA program encrypted in accordance with a particular encryption key and then writes the decrypted FPGA program into the FPGA. Thus an FPGA program encrypted in accordance with a particular encryption key can be used to program only those FPGAs coupled with a decryption circuit capable of decoding the encrypted FPGA program in accordance with that particular encryption key. Since the decryption circuit and the FPGA are implemented in the same IC, or within the same IC package, the decrypted FPGA program the decryption circuit produces cannot be readily intercepted and copied.
摘要翻译： 现场可编程门阵列（FPGA）和解密电路在公共集成电路（IC）内或在封装在公共IC封装内的单独的IC内实现。 解密电路解密根据特定加密密钥加密的输入FPGA程序，然后将解密的FPGA程序写入FPGA。 因此，可以使用根据特定加密密钥加密的FPGA程序来仅编程与根据该特定加密密钥解码加密的FPGA程序的解密电路耦合的那些FPGA。 由于解密电路和FPGA在相同的IC或相同的IC封装内实现，所以解密电路产生的解密的FPGA程序不容易被截取和复制。
-
2.发明授权Built-in spare row and column replacement analysis system for embedded memories 失效内置备用行和列替代分析系统，用于嵌入式存储器公开(公告)号：US06304989B1
公开(公告)日：2001-10-16
申请号：US09358689
申请日：1999-07-21
IPC分类号： G01R3128
CPC分类号： G11C29/72 , G11C29/44 , G11C29/4401
摘要： A built-in replacement analysis (BIRA) circuit allocates spare rows and columns of cells for replacing rows and columns of an array of memory cells in response to an input sequence of cell addresses, each identifying a row address and a column address of each defective cell of the cell array. The BIRA subsystem, including a row register corresponding each spare row and a column register corresponding to each spare column, responds to incoming cell addresses by writing their included row address into the row registers, by writing their column addresses into the column registers, and by writing link bits into the column registers. Each link bit links a row and a column register by storing row and column addresses of a defective cell. The BIRA subsystem also writes a “multiple cell” bit into each row register to indicate when the row address it stores includes more than one defective cell. The row and column addresses stored in these registers indicate the array rows and columns for which spare rows and columns are to be allocated. Each row and column register also includes a “permanent” bit the BIRA subsystem sets to indicate when the spare row or column allocation indicated by its stored row or column address is permanent. The BIRA subsystem efficiently allocates spare row and columns by manipulating the data stored in the row and column registers in response to a sequence of defective cell address.
摘要翻译： 内置替换分析（BIRA）电路分配备用的行和列单元格，以响应于单元地址的输入序列替换存储器单元阵列的行和列，每个单元地址标识每个缺陷的行地址和列地址 单元格的单元格。 BIRA子系统包括对应于每个备用行的行寄存器和与每个备用列相对应的列寄存器，通过将其包含的行地址写入行寄存器，通过将其列地址写入列寄存器，并通过 将链接位写入列寄存器。 每个链接位通过存储有缺陷单元的行和列地址来链接行和列寄存器。 BIRA子系统还将“多单元”位写入每个行寄存器，以指示其存储的行地址何时包括多个有缺陷的单元。 存储在这些寄存器中的行和列地址指示要为其分配备用行和列的数组行和列。 每个行和列寄存器还包括BIRA子系统设置的“永久”位，以指示由其存储的行或列地址指示的备用行或列分配是永久的。 BIRA子系统通过响应于有缺陷的单元地址的顺序操纵存储在行和列寄存器中的数据来有效地分配备用行和列。
-
公开(公告)号：US06587979B1
公开(公告)日：2003-07-01
申请号：US09494824
申请日：2000-01-31
IPC分类号： G11C2900
CPC分类号： G11C29/48 , G11C29/46 , G11C2029/1206 , G11C2207/104
摘要： A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.
摘要翻译： 灵活的内置自检（BIST）电路被集成到集成电路（IC）中，用于测试嵌入在集成电路中的一个或随机存取存储器或其他存储器，而不管存储器的数量，尺寸或测试要求如何。 来自控制器的输入数据可以方便地在IC内部和外部的组件之间分配，向BIST电路提供数据，指示要测试的嵌入式存储器的大小，并从多种BIST操作模式中进行选择。
-
4.发明申请CARRIER MODULE FOR ADAPTING NON-STANDARD INSTRUMENT CARDS TO TEST SYSTEMS 审中-公开用于将非标准仪器卡适用于测试系统的载体模块公开(公告)号：US20080157804A1
公开(公告)日：2008-07-03
申请号：US12048952
申请日：2008-03-14
IPC分类号： G01R1/20
CPC分类号： G01R31/31907
摘要： A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.
摘要翻译： 公开了能够将非标准仪表卡适配到测试系统架构的载体模块。 基于非标准架构的仪表卡可以组合在单个载体模块上。 载体模块然后插入测试系统的测试头。 载体模块提供包含在称为应用接口适配器（AIA）的插件子模块上的电路，用于在仪表卡和测试头接口连接器之间进行接口。 此外，AIA还可以提供从仪表卡到ATE系统校准电路的访问。 运营商模块使用测试系统的标准数据总线进行管理和控制功能。 第二辆公交车为非标准仪表卡提供总线。 仪器卡随附的软件驱动程序用适当的包装纸封装，以便卡片在测试系统的软件环境中无缝运行。
-
公开(公告)号：US5363810A
公开(公告)日：1994-11-15
申请号：US90288
申请日：1993-07-12
申请人： Lawrence Kraus
发明人： Lawrence Kraus
IPC分类号： A01K27/00
CPC分类号： A01K27/003
摘要： The animal control tether comprises an elongated body, first and second handles, and a clasping device. The elongated body has a first end section and a second, opposite end section. The first handle is located at the first end section of the elongated body for providing relatively distant control over an animal. The clasping device is affixed to the second end section of the elongated body. The second handle is located at the second end section. The second handle is constructed so as to remain slack, regardless of any tension exerted on the elongated body by an animal during use, until the second handle is grasped by an animal handler desiring close control over the animal's movements.
摘要翻译： 动物控制系绳包括细长体，第一和第二把手以及夹紧装置。 细长体具有第一端部和第二相对端部。 第一手柄位于细长主体的第一端部，用于提供对动物的相对较远的控制。 夹紧装置固定到细长主体的第二端部。 第二把手位于第二端部。 第二把手被构造成保持松弛，而不管动物在使用期间施加在细长身体上的任何张力，直到第二把手被动物处理者抓住，以期对动物的运动进行密切控制。
-
公开(公告)号：US07362089B2
公开(公告)日：2008-04-22
申请号：US10912848
申请日：2004-08-06
IPC分类号： G01R31/28
CPC分类号： G01R31/31907
摘要： A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.
-
7.发明授权Computer system and method for synthesizing a filter circuit for filtering out addresses greater than a maximum address 失效用于合成滤波器电路的计算机系统和方法，用于滤除大于最大地址的地址
公开(公告)号：US5930814A
公开(公告)日：1999-07-27
申请号：US697968
申请日：1996-09-03
摘要： A method and circuit are provided for generating a minimum-sized address filter to detect when the address space of an embedded memory having a smaller address space than another larger embedded memory is being exceeded. The method includes decomposing a maximum address into alternating sequences of consecutive binary ones (1's) and zeros (0's), discarding a final sequence if it contains binary 1's, and generating a filter circuit from a filter function formed from the alternating sequences of consecutive binary 1's and 0's. A built-in self test (BIST) circuit incorporating the address filter provides the ability to test a plurality of embedded memories at full speed in parallel. A computer system including a computer program for generating the filter circuit may also be provided.
摘要翻译： 提供了一种方法和电路，用于产生最小尺寸的地址过滤器，以便检测何时超出了具有比另一较大嵌入式存储器更小的地址空间的嵌入式存储器的地址空间。 该方法包括将最大地址分解为连续二进制（1）和零（0）的交替序列，如果包含二进制1则丢弃最终序列，并从由连续二进制的交替序列形成的滤波器函数生成滤波器电路 1和0。 结合地址滤波器的内置自测（BIST）电路提供了以全速并行测试多个嵌入式存储器的能力。 还可以提供包括用于生成滤波器电路的计算机程序的计算机系统。
-
公开(公告)号：US20080157805A1
公开(公告)日：2008-07-03
申请号：US12048990
申请日：2008-03-14
IPC分类号： G01R31/02
CPC分类号： G01R31/31907
摘要： A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.
-
公开(公告)号：US6085346A
公开(公告)日：2000-07-04
申请号：US697969
申请日：1996-09-03
摘要： A BIST function is provided in which both the routing area devoted to the test signals and the area devoted to the circuits required to implement the BIST routines are minimized, while also including the ability to test a plurality of embedded memories at full speed in parallel. Testing the memories at full speed both reduces test time and improves the quality of the testing.
摘要翻译： 提供了一种BIST功能，其中专用于测试信号的路由区域和专用于实现BIST例程所需的电路的区域最小化，同时还包括并行测试全部嵌入式存储器的能力。 以全速测试记忆可以减少测试时间，提高测试质量。
-
10.发明授权Method and apparatus for built-in self test of integrated circuits providing for separate row and column addresses 失效用于集成电路内置自检的方法和装置，提供单独的行和列地址
公开(公告)号：US6011748A
公开(公告)日：2000-01-04
申请号：US917013
申请日：1997-08-21
CPC分类号： G11C29/34
摘要： A BIST function is provided in which both the row address and the column address of a memory to be tested may be selected independently. The present invention provides flexibility in selecting addresses to be tested, improves transition time between rows, and allows determination of which memory address passes or fails the test.
摘要翻译： 提供BIST功能，其中可以独立地选择待测试的存储器的行地址和列地址。 本发明提供了选择要测试的地址的灵活性，改善了行之间的转换时间，并且允许确定哪个存储器地址通过或测试失败。
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.017 秒)
