METHODS AND SYSTEMS TO FACILITATE AUTHENTICATION OF A USER

    公开(公告)号:US20200014538A1

    公开(公告)日:2020-01-09

    申请号:US16026642

    申请日:2018-07-03

    申请人: Lawrence Liu

    发明人: Lawrence Liu

    IPC分类号: H04L9/32 H04L9/08 H04L9/14

    摘要: Disclosed is a method of facilitating authentication of a user. The method may include performing at least one of generating and receiving, using a processor, a primary cryptographic identifier consisted of a primary public key and a primary private key. Further, the method may include generating, using the processor, a global static user identifier corresponding to the user based on the primary public key. Further, the method may include generating, using the processor, a digital signature corresponding to a service based on a unique identifier associated with the service and the primary cryptographic identifier. Further, the method may include generating, using the processor, a key generation seed based on the digital signature and the global static user identifier. Further, the method may include generating, using the processor, a secondary cryptographic identifier including a secondary public key based on the key generation seed.

    System and method of authentication by leveraging mobile devices for expediting user login and registration processes online

    公开(公告)号:US10313881B2

    公开(公告)日:2019-06-04

    申请号:US15272381

    申请日:2016-09-21

    申请人: Lawrence Liu

    发明人: Lawrence Liu

    摘要: A method of authentication by leveraging mobile devices for expediting user login and registration processes provides a generic method for remotely authenticating login sessions using a portable computing device. An authentication initiation code (AIC) is generated and then displayed on the portable computing device. The AIC is inputted into a login feature of a relying party and a user entry is received through the login feature. An authentication request is sent to the portable computing device. User verification data is located for the relying party within a secure vault of personal identification data. The user is prompted to approve or deny the authentication request if the user verification data for the relying party is found within the secure vault. The user verification data is then used to grant access to restricted portions of the relying party if the authentication request is approved through the portable computing device.

    Methods, systems, apparatuses, and devices for providing durable forward confidentiality during communications between devices

    公开(公告)号:US11438315B1

    公开(公告)日:2022-09-06

    申请号:US17348616

    申请日:2021-06-15

    申请人: Lawrence Liu

    发明人: Lawrence Liu

    IPC分类号: H04L9/32 H04L9/40

    摘要: Disclosed herein is a method for providing durable forward confidentiality during communications between devices, in accordance with some embodiments. Accordingly, the method may include receiving an ephemeral entropy source identifier and a bit range identifier from a first user device, encrypting the ephemeral entropy source identifier and the bit range identifier, generating a ciphertext, transmitting the ciphertext to a second user device, receiving the ciphertext from the second user device, decrypting the ciphertext, obtaining the ephemeral entropy source identifier and the bit range identifier, identifying an ephemeral entropy source and a bit range, capturing a content from a stream of the ephemeral entropy source, generating a secret key using the content, identifying the ephemeral entropy source and the bit range, capturing the content from the stream, and generating the secret key using the content.

    Methods and systems to facilitate authentication of a user

    公开(公告)号:US10797879B2

    公开(公告)日:2020-10-06

    申请号:US16026642

    申请日:2018-07-03

    申请人: Lawrence Liu

    发明人: Lawrence Liu

    IPC分类号: H04L9/32 H04L9/08 H04L9/14

    摘要: Disclosed is a method of facilitating authentication of a user. The method may include performing at least one of generating and receiving, using a processor, a primary cryptographic identifier consisted of a primary public key and a primary private key. Further, the method may include generating, using the processor, a global static user identifier corresponding to the user based on the primary public key. Further, the method may include generating, using the processor, a digital signature corresponding to a service based on a unique identifier associated with the service and the primary cryptographic identifier. Further, the method may include generating, using the processor, a key generation seed based on the digital signature and the global static user identifier. Further, the method may include generating, using the processor, a secondary cryptographic identifier including a secondary public key based on the key generation seed.

    LASER MACHINING AND SCRIBING SYSTEMS AND METHODS
    5.
    发明申请
    LASER MACHINING AND SCRIBING SYSTEMS AND METHODS 审中-公开
    激光加工和切割系统和方法

    公开(公告)号:US20110132885A1

    公开(公告)日:2011-06-09

    申请号:US12962050

    申请日:2010-12-07

    IPC分类号: B23K26/00

    摘要: A laser machining system may include an opposite side camera to provide workpiece alignment from an opposite side of the system (i.e., the side opposite the laser machining process). The opposite side camera may be used with an air bearing positioning stage, and a portion of the stage and/or the opposite side camera may be moved to allow the opposite side camera to image a feature on the workpiece to be aligned. The opposite side alignment may be used with back side scribing and/or dual side scribing of a workpiece with alignment from one or both sides of the workpiece. Laser machining systems and methods may also be used to provide quasi-stealth scribing and multi-beam scribing.

    摘要翻译: 激光加工系统可以包括相对侧相机,以从系统的相对侧(即与激光加工过程相反的一侧)提供工件对准。 相对侧相机可以与空气轴承定位台一起使用,并且台架和/或相对侧相机的一部分可以被移动以允许相对侧相机对待对准的工件上的特征进行成像。 相对侧对准可以与来自工件的一侧或两侧对准的工件的背面划线和/或双面划线一起使用。 激光加工系统和方法也可用于提供准隐形划线和多光束划线。

    Method and structure in the manufacture of mask read only memory
    6.
    发明授权
    Method and structure in the manufacture of mask read only memory 有权
    掩膜只读存储器的制造方法和结构

    公开(公告)号:US07244653B2

    公开(公告)日:2007-07-17

    申请号:US10807795

    申请日:2004-03-23

    申请人: Lawrence Liu Yuan Kao

    发明人: Lawrence Liu Yuan Kao

    IPC分类号: H01L27/76

    CPC分类号: H01L27/112 H01L27/1126

    摘要: A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, a second dielectric layer having a plurality of contact plugs is formed on the semiconductor structure, wherein the contact plug comprises a second dielectric layer and a first glue layer, furthermore; the first glue layer is placed on the side-wall and bottom of the contact plugs. In addition, the contact plugs filled with the first metal layer. Then, a second glue layer, a second metal layer and a pad layer having an opening pattern are respectively formed on the second dielectric layer and contact plug. Thus, the processes of the present invention can improve the stability and accuracy in the electricity of the mask ROM device.

    摘要翻译: 提供了掩模ROM器件的制造方法和结构。 首先,提供半导体结构,其包括第一介电层,多个掩埋位线和多个代码区域,其中每个代码区域被放置在两个掩埋位线之间。 接下来,在半导体结构上形成具有多个接触插塞的第二电介质层,其中,所述接触插塞还包括第二电介质层和第一胶合层; 第一胶层位于接触塞的侧壁和底部。 另外,填充有第一金属层的接触塞子。 然后,在第二电介质层和接触插塞上分别形成具有开口图案的第二胶合层,第二金属层和垫层。 因此,本发明的方法可以提高掩模ROM装置的电力的稳定性和精度。

    Method and structure in the manufacture of mask read only memory
    7.
    发明申请
    Method and structure in the manufacture of mask read only memory 有权
    掩膜只读存储器的制造方法和结构

    公开(公告)号:US20050224892A1

    公开(公告)日:2005-10-13

    申请号:US10807795

    申请日:2004-03-23

    申请人: Lawrence Liu Yuan Kao

    发明人: Lawrence Liu Yuan Kao

    CPC分类号: H01L27/112 H01L27/1126

    摘要: A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, a second dielectric layer having a plurality of contact plugs is formed on the semiconductor structure, wherein the contact plug comprises a second dielectric layer and a first glue layer, furthermore; the first glue layer is placed on the side-wall and bottom of the contact plugs. In addition, the contact plugs filled with the first metal layer. Then, a second glue layer, a second metal layer and a pad layer having an opening pattern are respectively formed on the second dielectric layer and contact plug. Thus, the processes of the present invention can improve the stability and accuracy in the electricity of the mask ROM device.

    摘要翻译: 提供了掩模ROM器件的制造方法和结构。 首先,提供半导体结构,其包括第一介电层,多个掩埋位线和多个代码区域,其中每个代码区域被放置在两个掩埋位线之间。 接下来,在半导体结构上形成具有多个接触插塞的第二电介质层,其中,所述接触插塞还包括第二电介质层和第一胶合层; 第一胶层位于接触塞的侧壁和底部。 另外,填充有第一金属层的接触塞子。 然后,在第二电介质层和接触插塞上分别形成具有开口图案的第二胶合层,第二金属层和垫层。 因此,本发明的方法可以提高掩模ROM装置的电力的稳定性和精度。

    I/O bias circuit insensitive to inadvertent power supply variations for
MOS memory
    8.
    发明授权
    I/O bias circuit insensitive to inadvertent power supply variations for MOS memory 失效
    I / O偏置电路对MOS存储器无意的电源变化不敏感

    公开(公告)号:US5949722A

    公开(公告)日:1999-09-07

    申请号:US62175

    申请日:1998-04-16

    IPC分类号: G11C7/10 G11C11/4096 G11C7/00

    摘要: An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off. During this period, the biasing circuit interacts with the memory cell to bias the first node to a potential corresponding to the state of the memory cell. Also during the second period of time the sense amplifier is enabled to detect the state of the memory cell by sensing the potential on the first node.

    摘要翻译: 在MOS存储器件中使用的输入/输出偏置电路对无意的电源变化不敏感。 被编程为给定状态的存储器单元具有连接到第一节点的终端。 第一个MOS开关,常开,连接在第一个节点和一个接地端子之间。 常闭的偏置电路和第二MOS开关连接在电源端子和第一节点之间。 第一节点连接到读出放大器的两个输入端之一,第二输入端连接到读出放大器使能/禁止信号。 在选择存储单元时,第一开关被接通并且第二开关在第一时间段被关闭。 在此期间,偏置电路和第一开关相互作用以将第一节点偏置到等于低于电源电压的一个阈值电压的电位。 在第一时间段之后的第二时间段内,两个开关1和2都断开。 在此期间,偏置电路与存储器单元交互以将第一节点偏置到与存储器单元的状态相对应的电位。 而且在第二时段期间,读出放大器能够通过感测第一节点上的电位来检测存储器单元的状态。

    I/O bias circuit insensitive to inadvertent power supply variations for
MOS memory

    公开(公告)号:US5812474A

    公开(公告)日:1998-09-22

    申请号:US733858

    申请日:1996-10-18

    IPC分类号: G11C7/10 G11C7/02

    CPC分类号: G11C7/1048

    摘要: An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off. During this period, the biasing circuit interacts with the memory cell to bias the first node to a potential corresponding to the state of the memory cell. Also during the second period of time the sense amplifier is enabled to detect the state of the memory cell by sensing the potential on the first node.