公开(公告)号：US20080098266A1

公开(公告)日：2008-04-24

申请号：US11954403

申请日：2007-12-12

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318558

摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

摘要翻译： 本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。 总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。 总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。 本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。 在本公开的第五方面中，一种接口选择电路， 图41-49提供了选择性地使用图5的5信号接口。 41或图3的3信号接口。 8。

公开(公告)号：US20080094104A1

公开(公告)日：2008-04-24

申请号：US11874714

申请日：2007-10-18

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： H03K19/0175

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/318544 ,  G01R31/318547 ,  G11C29/48

摘要： A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

摘要翻译： 一种过程和装置提供一种JTAG TAP控制器（302），以使用减少的引脚数，高速DDR接口（202）来访问设备的JTAG TAP域（106）。 通过将来自TAP控制器的单独TDI和TMS信号组合成单个信号并在驱动DDR接口的TCK的上升沿和下降沿传送单个信号的TDI和TMS信号来实现接入。 TAP域可以以点对点方式或以可寻址总线方式耦合到TAP控制器。 对TAP域的访问可用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

公开(公告)号：US20080059855A1

公开(公告)日：2008-03-06

申请号：US11936884

申请日：2007-11-08

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/3177 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318572

摘要： A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

摘要翻译： TAP链接模块（21,51）允许通过单个TAP接口（20）从测试总线（13）控制和访问多个TAP（TAP 1-4）。

公开(公告)号：US20070300109A1

公开(公告)日：2007-12-27

申请号：US11833088

申请日：2007-08-02

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G06F11/25

CPC分类号： G01R31/31717 ,  B82Y25/00 ,  G01R31/31701 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318572 ,  G01R33/093

摘要： A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

摘要翻译： 传播测试指令，衰减测试指令和循环测试指令提供包括JTAG边界扫描单元在内的电路之间的直流和交流互连电路的测试。 测试访问端口电路的一些补充，包括门控产生捕捉测试频闪（CTS）信号和边界扫描单元需要实施附加说明。 说明书是常规JTAG操作结构的扩展。

公开(公告)号：US20070294606A1

公开(公告)日：2007-12-20

申请号：US11847747

申请日：2007-08-30

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/311

CPC分类号： G01R31/3177 ,  G01R31/318505 ,  G01R31/318544

摘要： Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell. The inputs of the additional multiplexer connect to the data input and data output of the boundary cell.

摘要翻译： 通过使用从诸如电路1的一个电路输出的扫描测试响应数据作为诸如电路2的另一个电路的扫描测试激励数据来加速诸如电路1到N的多个目标电路的扫描测试。 复位后，扫描路径从所有电路的复位激励中捕获输出响应数据。 然后，测试者将捕获的数据仅移动第一电路的扫描路径的长度，同时用新的测试激励数据加载第一电路的扫描路径。 然后在扫描路径中捕获来自所有电路的新的响应数据。 重复该移位和捕获周期直到第一个电路被测试。 然后禁用第一电路，并且将任何剩余的激励数据施加到第二电路。 重复该过程直到所有电路都被测试。 在扫描测试中使用的数据保留边界扫描单元将附加多路复用器的输出连接到边界单元的输入。 附加多路复用器的输入连接到边界单元的数据输入和数据输出。

公开(公告)号：US20070229114A1

公开(公告)日：2007-10-04

申请号：US11759025

申请日：2007-06-06

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： H03K19/173

CPC分类号： G01R31/3177 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318508 ,  G01R31/318555

摘要： A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores.—The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

摘要翻译： 测试架构使用链接指令寄存器（LIR）访问IC内的IP核测试包装器。 正在开发IEEE P1500标准，通过称为包装器的测试结构提供对这些单独内核的测试访问。 包装器位于核心的边界处，并提供了一种测试核心和核心之间的互连的方法。测试架构使得IC中的多个包装器中的每个包括嵌入在其他核心内的核心中的包装器，具有单独的使能信号 。

公开(公告)号：US20070118780A1

公开(公告)日：2007-05-24

申请号：US11626710

申请日：2007-01-24

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/318563 ,  G01R31/318572

摘要： An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

摘要翻译： 集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。 这些端口的访问和控制是一个测试链接模块。 集成电路上的测试访问端口可以以一个测试链接模块来控制对多个辅助测试链接模块和测试访问端口的访问的层次结构。 每个次级测试链接模块依次也可以控制对三级测试链接模块和测试访问端口的访问。 测试链接模块也可用于仿真。

公开(公告)号：US20070103205A1

公开(公告)日：2007-05-10

申请号：US11555349

申请日：2006-11-01

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： H03B1/00

CPC分类号： H03K19/01759 ,  H04L25/0272

摘要： First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

摘要翻译： 第一和第二设备可以使用仅一对LVDS信号路径彼此双向地进行通信。 每个器件包括连接到单对LVDS信号路径的输入电路和差分输出驱动器。 输入电路的输入端也连接到驱动器的输入端。 输入电路还可以接收偏移电压。 响应于其输入，每个设备中的输入电路可以使用比较器，门和多路复用器来确定通过来自另一个设备的一对LVDS信号路径传输的逻辑状态。 这有利地将第一和第二设备之间所需的互连的数目减少了一半。

公开(公告)号：US20060064613A1

公开(公告)日：2006-03-23

申请号：US11273754

申请日：2005-11-15

申请人： Lee Whetsel

发明人： Lee Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/3172 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318572 ,  G06F1/10

摘要： Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation/debug circuitry, and IEEE P1532 in-system programming circuitry. Internal scan test ports serve as a serial communication port for primarily accessing internal scan circuitry within ICs and cores. Today, the TAP and internal scan test ports are typically viewed as being separate test interfaces, each utilizing different IC pins and/or core terminals. The need for different IC pins and/or core terminals is overcome by an interface in accordance with the invention that allows the TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core terminals. Further, this interface allows merged TAP and scan test port interfaces to be selected individually or in groups.

摘要翻译： IEEE 1149.1测试访问端口（TAP）接口和内部扫描测试端口存在IC和/或内核的两种常见的测试接口。 TAP用作用于访问各种电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内建自测电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真/调试电路和IEEE P1532系统编程电路。 内部扫描测试端口用作主要访问IC和内核内部扫描电路的串行通信端口。 今天，TAP和内部扫描测试端口通常被视为分离的测试接口，每个测试接口都使用不同的IC引脚和/或核心端子。 通过根据本发明的接口来克服对不同IC引脚和/或核心端子的需要，其允许TAP和内部扫描测试端口被合并，使得它们可以从同一组IC引脚共存和操作， /或核心终端。 此外，该接口允许单独或分组选择合并的TAP和扫描测试端口接口。

公开(公告)号：US20050204228A1

公开(公告)日：2005-09-15

申请号：US11103783

申请日：2005-04-11

申请人： Lee Whetsel ,  Joel Graber

发明人： Lee Whetsel ,  Joel Graber

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/31721 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318547 ,  G01R31/318575 ,  G01R31/31858 ,  G01R31/318586

摘要： Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present invention improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

摘要翻译： 扫描和扫描BIST架构通常用于测试集成电路中的数字电路。 本发明改进了低功率扫描和扫描BIST方法。 该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。