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    Forming electrical connections for electronic devices
    3.
    发明授权
    Forming electrical connections for electronic devices 失效
    形成电子设备的电气连接

    公开(公告)号：US4946550A

    公开(公告)日：1990-08-07

    申请号：US313661

    申请日：1989-02-21

    申请人： Josephus M. F. G. Van Laarhoven

    发明人： Josephus M. F. G. Van Laarhoven

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768

    CPC分类号： H01L21/76819

    摘要： A method is described for providing insulating material on an electrically conductive level (1) of a substructure (10) forming part of an electronic device, which electrically conductive level has at least two spaced-apart electrically conductive regions (1a,1b). Insulating material (2,3) is provided over the electricaly conductive level (1) to a thickness insufficient for insulating material on adjacent conductive regions (1a,1b) to meet thereby leaving a recess (4) in the insulating material between the conductive regions (1a,1b). Next a planarising medium (5) is applied onto the insulating material (2,3) and etched so as to expose a top surface (3a) of the insulating material (2,3) thereby leaving planarising medium (5a) in the recess (4). The insulating material (2,3) is then etched anisotropically using the remaining planarising medium (5a,5b) as a mask so that the surface (11) of the electrically condutive level (1) is exposed. The etching of the insulating material ( 2,3) is controlled so that the insulating material is etched away just down to the bottom (50a) of the planarising medium (5a) in the recess (4) and the remaining planarising medium (5a,5b) is then removed so as to leave the surface of the substructure (10) between the electrically conductive regions (1a,1b) covered by a relatively flat layer (30) of insulating material. A further layer (6), for example of insulating mateirl, is then deposited onto the remaining relatively flat layer of insulating material.

    Method of manufacturing a semiconductor device
    4.
    发明授权
    Method of manufacturing a semiconductor device 失效

    公开(公告)号：US4956312A

    公开(公告)日：1990-09-11

    申请号：US354001

    申请日：1989-05-19

    申请人： Josephus M. F. G. Van Laarhoven

    发明人： Josephus M. F. G. Van Laarhoven

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768

    CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76831 ,  Y10S148/051

    摘要： A method of manufacturing a semiconductor device is described in which electrical contact is provided to an area (10) of an electrically conductive level (1) exposed through an opening (2) in a covering layer (3). A further layer is provided over the covering layer (3) as a first layer (4) of one material provided to a first thickness on the covering layer (3) and a second layer (5) of a different material provided to a second thickness on the first layer. The further layer is then etched anisotropically using an anisotropic etching process which etches the first and second layers (4) and (5) at different rates with the first layer (4) being etched more slowly than the second layer (5) so that, after anisotropic etching to expose the surface (3a) of the covering layer (3) and the area (10) of the electrically conductive level (1), the side walls (2a) of the opening (2) remain covered by the one material (40 ) and portions (50) of the different material extend on the one material (40) from the exposed area (10) up the side walls (2a) of the opening (2) for a distance less than the depth of the opening (2) in relation to the thickness of the first layer and the different rates at which the first and second layers 4 and 5 are etched. An electrically conductive layer (6) is then provided on the covering layer (3) to form an electrical contact with the exposed area (10) of the electrically conductive level (1).