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    Antimicrobial composition
    1.
    发明申请
    Antimicrobial composition 审中-公开
    抗微生物组成

    公开(公告)号：US20070048345A1

    公开(公告)日：2007-03-01

    申请号：US11364799

    申请日：2006-02-28

    申请人： Lei Huang ,  Shu-Ping Yang ,  Ali Yahiaoui ,  Anthony Spencer

    发明人： Lei Huang ,  Shu-Ping Yang ,  Ali Yahiaoui ,  Anthony Spencer

    IPC分类号： A01N43/40 ,  A01N25/00 ,  A01N37/30

    CPC分类号： A01N31/02 ,  A01N25/30 ,  A01N33/12 ,  A01N43/40 ,  A01N47/44 ,  A01N2300/00

    摘要： An antimicrobial composition that contains an antimicrobial agent and a sugar alcohol is provided. The sugar alcohol is more generally more biocompatible and biodegradable than the antimicrobial agent. In addition, without intending to be limited by theory, it is believed that sugar alcohols increase the attraction of the antimicrobial agent to microorganisms (e.g., the cytoplasmic membrane of bacteria). Because a greater percentage of the antimicrobial agent molecules are brought into contact with the microorganisms, the efficiency of growth inhibition is increased. Thus, the antimicrobial composition provides good efficacy without the need for high levels of an antimicrobial agent.

    摘要翻译： 提供了含有抗微生物剂和糖醇的抗微生物组合物。 糖醇通常比抗微生物剂更生物相容性和生物降解性。 此外，不希望受理论限制，据信糖醇增加了抗微生物剂对微生物（例如细菌的细胞质膜）的吸引力。 因为较大比例的抗微生物剂分子与微生物接触，所以生长抑制的效率增加。 因此，抗微生物组合物提供良好的效力，而不需要高水平的抗微生物剂。

    Antimicrobial composition
    2.
    发明申请
    Antimicrobial composition 审中-公开
    抗微生物组成

    公开(公告)号：US20070048344A1

    公开(公告)日：2007-03-01

    申请号：US11216800

    申请日：2005-08-31

    申请人： Ali Yahiaoui ,  Phillip Schorr ,  Douglas Hoffman ,  David Koenig ,  Anthony Spencer ,  Angela Dobson

    发明人： Ali Yahiaoui ,  Phillip Schorr ,  Douglas Hoffman ,  David Koenig ,  Anthony Spencer ,  Angela Dobson

    IPC分类号： A01N57/00 ,  A01N43/80 ,  A01N25/00 ,  A01N43/04

    CPC分类号： C08K5/0058 ,  C08K5/31

    摘要： An antimicrobial composition that involves a synergistic mixture in terms of active agents, of a primary antimicrobial agent, such as polyhexamethylene biguanide (PHMB), a secondary antimicrobial agent, and optionally an organic acid against various kinds of microbes is described. Various additional processing aids, such as alcohols and surfactants, may also be incorporated within the mixture. The composition allows one to use a significantly less concentration of individual constituent antimicrobial agents to achieve the same or a better degree of antimicrobial efficacy. The antimicrobial composition can be applied to the surface of almost any kind of substrate material, and can achieve a killing-efficacy of about 3 Log10 reduction in microbes within 30 minutes under ambient conditions.

    摘要翻译： 描述了关于活性剂，主要抗微生物剂如聚六亚甲基双胍（PHMB），二次抗微生物剂和任选的针对各种微生物的有机酸的协同混合物的抗微生物组合物。 各种其它加工助剂，如醇和表面活性剂，也可以掺入混合物中。 该组合物允许使用显着较少浓度的单个成分抗微生物剂以达到相同或更好程度的抗微生物效力。 抗微生物组合物可以应用于几乎任何种类的底物材料的表面，并且可以在环境条件下在30分钟内实现微生物中约3log 10/10的还原的杀伤效力。

    Packet storage system for traffic handling
    6.
    发明申请
    Packet storage system for traffic handling 有权
    用于流量处理的分组存储系统

    公开(公告)号：US20050265368A1

    公开(公告)日：2005-12-01

    申请号：US10534343

    申请日：2003-11-11

    申请人： Anthony Spencer

    发明人： Anthony Spencer

    IPC分类号： H04L12/54 ,  H04L12/823 ,  H04L12/851 ,  H04L12/861 ,  H04L12/863 ,  H04L12/869 ,  H04L12/875 ,  H04L12/56

    CPC分类号： H04L47/32 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/562 ,  H04L47/60 ,  H04L47/6215 ,  H04L47/624 ,  H04L49/90 ,  H04L49/9042

    摘要： A method of queuing variable size data packets in a communication system comprises generating from an incoming data packet a record portion of predetermined fixed size and containing information about the packet, the data in the packet being in a data portion; storing data portions in independent memory locations in a first memory with each data portion having no connection with any other; storing record portions in one or more managed queues in a second memory having fixed size memory locations equal in size to the size of the record portions; wherein: the first memory is larger and has a lower address bandwidth than the second memory; and the memory locations in the first memory are arranged in blocks having a plurality of different sizes and the memory locations are allocated to the data portions according to the size of the data portions. Conveniently, there may be two sizes of memory location in the first memory arranged in two blocks, one of a size to receive relatively small data portions and the other of a size to receive relatively large data portions. Data portions that are too large to be stored in a single memory block are stored as linked lists in a plurality of blocks with pointers pointing to the next block but without any pointers pointing from one data portion to the next data portion of the packet. The memory locations in the blocks are preferably matched to the most commonly occurring sizes of data packets in the communication system. The memory locations in the first memory are preferably allocated from a pool of available addresses provided to it in batches from a central pool of available addresses.

    摘要翻译： 在通信系统中排队可变大小数据分组的方法包括从输入数据分组生成预定固定大小的记录部分并且包含关于分组的信息，分组中的数据在数据部分中; 将数据部分存储在第一存储器中的独立存储器位置，其中每个数据部分与任何其他数据部分没有连接; 将记录部分存储在具有与记录部分的大小相等的固定大小的存储单元的第二存储器中的一个或多个托管队列中; 其中：所述第一存储器较大并且具有比所述第二存储器低的地址带宽; 并且第一存储器中的存储器位置被布置成具有多个不同大小的块，并且根据数据部分的大小将存储器位置分配给数据部分。 方便地，在第一存储器中可以存在两个尺寸的存储器位置，其布置在两个块中，其中一个尺寸用于接收相对较小的数据部分，另一个尺寸用于接收相对大的数据部分的大小。 太大而不能存储在单个存储器块中的数据部分作为链表存储在具有指向下一个块的指针的多个块中，但是没有从一个数据部分指向分组的下一个数据部分的任何指针。 块中的存储器位置优选地与通信系统中最常发生的数据分组大小匹配。 优选地，从可用地址的中央池批量地从提供给它的可用地址池分配第一存储器中的存储器位置。

    Traffic management architecture
    7.
    发明申请
    Traffic management architecture 审中-公开
    交通管理架构

    公开(公告)号：US20050243829A1

    公开(公告)日：2005-11-03

    申请号：US10534346

    申请日：2003-11-11

    申请人： Anthony Spencer

    发明人： Anthony Spencer

    IPC分类号： H04L12/54 ,  H04L12/823 ,  H04L12/851 ,  H04L12/861 ,  H04L12/863 ,  H04L12/869 ,  H04L12/875 ,  H04L12/56

    CPC分类号： H04L47/32 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/562 ,  H04L47/60 ,  H04L47/6215 ,  H04L47/624 ,  H04L49/90 ,  H04L49/9042

    摘要： An architecture for sorting incoming data packets in real time, on the fly, processes the packets and places them into an exit order queue before storing the packets. This is in contrast to the traditional way of storing first then sorting later and provides rapid processing capability. A processor generates packet records from an input stream and determines an exit order number for the related packet. The records are stored in an orderlist manager while the data portions are stored in a memory hub for later retrieval in the exit order stored in the manager. The processor is preferably a parallel processor array using SIMD and is provided with rapid access to a shared state by a state engine.

    摘要翻译： 一个用于实时分类传入数据包的架构，在处理数据包之前，将它们存储到一个出口订单队列中，然后再存储数据包。 这与先前存储的传统方式相反，然后进行排序，并提供快速的处理能力。 处理器从输入流产生分组记录，并确定相关分组的出口订单编号。 记录被存储在订单列表管理器中，同时数据部分存储在存储器集线器中，用于随后在存储在管理器中的退出顺序中检索。 处理器优选地是使用SIMD的并行处理器阵列，并且被状态引擎提供到快速访问共享状态。

    Data packet handling in computer or communication systems
    8.
    发明授权
    Data packet handling in computer or communication systems 有权
    计算机或通信系统中的数据包处理

    公开(公告)号：US07522605B2

    公开(公告)日：2009-04-21

    申请号：US10534308

    申请日：2003-11-11

    申请人： Anthony Spencer ,  Ken Cameron

    发明人： Anthony Spencer ,  Ken Cameron

    IPC分类号： H04L12/28

    CPC分类号： H04L47/32 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/562 ,  H04L47/60 ,  H04L47/6215 ,  H04L47/624 ,  H04L49/90 ,  H04L49/9042

    摘要： The ordering of packet flows, comprising sequences of data packets, in a communication or computer system, is performed by assigning an exit number to each packet; queuing the packets in a buffer; and outputting the queued packets in a predetermined order according to an order list determined by the exit numbers assigned to each packet before it was queued. The exit number information is preferably assigned to packet records, which are queued in a separate buffer to the packets, the records being of fixed length and shorter than the data portions. The packet record buffer comprises groups of bins, each bin containing a range of exit numbers, the bins for higher exit number packet records having a larger range than bins for lower exit number packet records. Lower exit number packet records in a bin are subdivided into a plurality of bins, each containing packet records corresponding to a smaller range of exit numbers. Secondary bins may be created to temporarily store records assigned to a bin that is currently being emptied. The bins may be filled by a parallel processor, preferably a SIMD array processor.

    摘要翻译： 在通信或计算机系统中包括数据分组序列的分组流的排序通过向每个分组分配出口号码来执行; 在缓冲区中排队数据包; 并且根据由分配给每个分组排队之前的出口号确定的顺序列表，以预定顺序输出排队的分组。 出口号信息优选地被分配给分组记录，分组记录在分组的单独缓冲器中排队，记录具有固定长度并且短于数据部分。 分组记录缓冲器包括一组分组，每个分组包含一个出口编号的范围，用于较高出口编号分组记录的分段具有比用于较低出口编号分组记录的分段大的范围。 一个存储区中的较低出口数量的数据包记录被细分为多个存储区，每个存储区包含对应于较小范围的退出编号的数据包记录。 可以创建辅助箱以临时存储分配给当前正在清空的仓的记录。 盒可以由并行处理器，优选地是SIMD阵列处理器来填充。

    State engine for data processor
    10.
    发明申请
    State engine for data processor 有权
    数据处理器的状态引擎

    公开(公告)号：US20050257025A1

    公开(公告)日：2005-11-17

    申请号：US10534430

    申请日：2003-11-11

    申请人： Anthony Spencer

    发明人： Anthony Spencer

    IPC分类号： H04L12/54 ,  H04L12/823 ,  H04L12/851 ,  H04L12/861 ,  H04L12/863 ,  H04L12/869 ,  H04L12/875 ,  G06F15/00

    CPC分类号： H04L47/32 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/562 ,  H04L47/60 ,  H04L47/6215 ,  H04L47/624 ,  H04L49/90 ,  H04L49/9042

    摘要： Coherent accesses and updates to state shared by parallel processors, such as SIMD array processors, is made possible by the use of state elements having local memory storing the state and permitting serialisation of accesses. Operations on single or multiple items of state are perfumed by a fixed/hardwired set of operations but they can be programmable by sending command and data to control operations. Individual state elements comprise the local memory, an arithmetic unit, and command and control logic. Multiple state elements are pipelined in state cells which can, in turn, be organised into state arrays and state engines effecting complete control over shared state access. A read/modify/write operation can be performed in only two cycles and a complete command in only three to five cycles.

    摘要翻译： 通过使用具有存储状态的本地存储器并允许访问序列化的状态元素，可以实现对诸如SIMD阵列处理器之类的并行处理器共享的状态的相干访问和更新。 单个或多个状态的操作通过固定/硬连线的操作进行加密，但是可以通过发送命令和数据来编程控制操作。 各个状态元素包括本地存储器，算术单元以及命令和控制逻辑。 多个状态元素在状态单元中被流水线化，状态单元又可以被组织成状态数组，并且状态引擎完全控制共享状态访问。 读/修改/写操作只能在两个周期内完成，只需三到五个周期即可完成命令。